Method and means for minimizing the effect of short circuits in

Details Method and means for minimizing the effect of short circuits in Method and means for minimizing the effect of short circuits in

1981-09-30

1983-09-27

Curtis, Marshall M.

Communications: electrical

Land vehicle alarms or indicators

Internal alarm or indicator responsive to a condition of the...

307200B, 365200, 34082586, 340781, G09G 332

Patent

active

044069979

ABSTRACT:
A flat panel display device comprising a matrix of X and Y drive lines and a plurality of selecting field effect transistors (FETs) is described. Each FET is selectively operable by applying a potential across a unique pair of X and Y drive lines for controlling activation of a corresponding optical transducer. A high value resistance is interposed in series between the gate electrode of each selecting FET and associated drive line to minimize the effect a short circuit caused by a defective gate electrode establishing an electrical connection between X and Y drive lines. The resistance is preferably provided by a segment of undoped polysilicon on a polysilicon circuit line connecting each gate electrode with the associated X drive line.

REFERENCES:
patent: 3631251 (1971-12-01), Lehovic
patent: 3655996 (1972-04-01), Takahashi
patent: 3754171 (1973-08-01), Anzai et al.
patent: 4027173 (1977-05-01), Nomiya et al.
patent: 4209713 (1980-06-01), Satou et al.
Dynamically Pulsed Gate Lines to Overcome Gate Shorts in Nonvolatile Technology; IBM Tech. Discl. Bull.; vol. 17, No. 7; 12/74; pp. 1889-1890; Leung.
"Liquid Crystal Driver Circuit and Polysilicon Components Therefor", IBM Technical Disclosure Bulletin, vol. 23, #8, Jan. 1981, pp. 3863-3864.

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