Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
2000-05-01
2002-07-09
Gaffin, Jeffrey (Department: 2841)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C361S794000, C361S782000, C361S793000, C361S792000, C361S780000, C174S255000, C333S246000, C333S247000, C333S219000
Reexamination Certificate
active
06418031
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to printed circuit boards and, in particular, to an improved method and means for decoupling parallel planes included within a printed circuit board. Still more particularly, the present invention relates to a method and means for decoupling parallel planes included within a printed circuit board utilizing a first plurality of decoupling elements in a first region of the planes and a second plurality of decoupling elements in a second region of the planes.
2. Description of the Related Art
The inclusion of a capacitive decoupling network between the power and ground planes of a printed circuit board (PCB) is well known and desirable for a number of reasons. Specifically, decoupling capacitors may be provided in the form of discrete decoupling capacitors connected between the power and ground planes of the PCB, the discrete decoupling capacitors being located adjacent to loads, which typically comprise integrated circuits (ICs) mounted on the PCB. Decoupling capacitance is also provided in the form of intrinsic capacitance by the parallel location of the power and ground planes with a PCB. This decoupling capacitance serves to provide fast rise time current to the integrated circuit (IC) loads and to minimize differential voltages that may develop between the power and ground planes of the PCB as a result of IC switching events by isolating the switching currents as local events. This in turn reduces the potential of the PCB to radiate and conduct electromagnetic interference (EMI).
FIG. 1
shows an equivalent circuit
10
for an integrated circuit
12
and a decoupling capacitor (C
d
)
14
mounted on a PCB. The intrinsic, or interplanar, capacitance is represented by the capacitor (C
0
)
16
. The power plane is represented by the line
18
, and the ground plane by line
20
.
The power plane of a PCB should ideally exhibit zero impedance. It is desirable to minimize the impedance of power planes as much as possible.
FIG. 2
is a graph showing power plane impedance (Z) versus frequency (MHz) for an example power and ground plane pair within a PCB having a single type of discrete decoupling capacitors mounted thereon. The graph plots the impedance of the power plane, with the PCB configured as a “bare board” (i.e. a PCB without any discrete capacitors mounted thereon), with broken line
22
, and the impedance of the power plane, with the PCB having the single type of discrete decoupling capacitors mounted thereon, with solid line
24
. As is apparent from the graph, the impedance increases dramatically at operating frequencies above a series resonant frequency (f
1
) due, inter alia, to the presence of the discrete decoupling capacitors, and the impedance theoretically becomes infinite at a parallel resonant frequency (f
2
). The impedance of a PCB employing a single type of discrete decoupling capacitors comprises the cumulative impedance of the power and ground planes, vias connecting these planes, traces between capacitors and ICs, and the capacitor mounting pads. The significant increases in the power plane impedance at high frequencies results in the performance of the PCB deteriorating substantially at these frequencies, at which the PCB may not function properly, or may exceed regulatory emission levels.
The series resonant frequency (f
1
) is determined mainly by the number and location of the single type of discrete decoupling capacitors. By optimizing the number and location of the single type of discrete decoupling capacitors, as well as other PCB characteristics, it is possible to shift the series resonant frequency (f
1
) to higher frequencies as increased operating frequencies are encountered. However, PCB operating frequencies are being achieved at which it has become increasingly difficult, inefficient, and expensive to match the series resonant frequency (f
1
) to the PCB operating frequency. Computers are now operating at clock rates much higher than was possible in the past. This results in the creation of high frequency harmonic energy in the hundreds of megahertz, and even into the gigahertz region.
A “Q-factor” may be determined for a resonant structure, such as a structure included within a printed circuit board. The “Q-factor” of a resonant structure is based on the amount of loss in the structure. The higher the amount of loss, the lower the “Q-factor” becomes. In the case of a simple parallel power and ground plane structure there is little loss. Therefore, the “Q-factor” is high. This would normally result in higher EMC emissions.
Therefore a need exists for an improved method and means for decoupling parallel planes included within a printed circuit board both at low-level as well as high-level frequencies.
SUMMARY OF THE INVENTION
An improved method and means for decoupling a printed circuit board are disclosed. A power plane is included having a peripheral edge. The power plane includes a first region and a second region which is separate from and contiguous to the first region. The first region is located from the peripheral edge to a middle portion of the power plane. The first region includes a peripheral portion of the power plane. The second region includes only the middle portion of the power plane. A ground plane is coupled in parallel to the power plane. The ground plane has a peripheral edge. The ground plane includes a first region, and a second region which is separate from and contiguous to the first region. The first region includes the peripheral edge and includes a peripheral portion of the ground plane. The second region includes a middle portion of the ground plane. A first plurality of decoupling elements are connected to the first region of the power plane and to the first region of the ground plane. A second plurality of decoupling elements are connected to the second region of the power plane and to the second region of the ground plane. The first and second plurality of decoupling elements are utilized to decouple the power plane and ground plane pair.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 4916576 (1990-04-01), Herbert et al.
patent: 5089878 (1992-02-01), Lee
patent: 5479138 (1995-12-01), Kuroda et al.
patent: 5556811 (1996-09-01), Agatstein et al.
patent: 5825628 (1998-10-01), Garbelli et al.
patent: 5898576 (1999-04-01), Lockwood et al.
patent: 6166457 (2000-12-01), Iguchi et al.
patent: 6198362 (2001-03-01), Harada et al.
patent: 6211576 (2001-04-01), Shimizu et al.
Bui Hung
Gaffin Jeffrey
International Business Machines - Corporation
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