Pulse or digital communications – Miscellaneous
Reexamination Certificate
2000-01-04
2003-09-16
Corrielus, Jean B. (Department: 2631)
Pulse or digital communications
Miscellaneous
C713S400000, C327S141000
Reexamination Certificate
active
06621883
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and apparatus for data detection from a bus utilizing double transition clocking data transfers. More particularly, the present invention relates to a method and apparatus for detecting data on an SCSI bus as defined in the SCSI Ultra-3 specification.
BACKGROUND OF THE INVENTION
The Small Computer System Interface (SCSI) encompasses a set of evolving ANSI standard electronic interfaces that allow personal computers to communicate with peripheral hardware such as disk drives, tape drives, CD-ROM drives, printers, etc. The original SCSI, commonly referred to as SCSI-1, evolved into SCSI-2, commonly referred to as “plain SCSI” due to its overwhelming adoption by the computing community. SCSI-3 expands on SCSI-2 to include a set of primary commands and additional specialized command sets to meet the needs of specific device types. A widely implemented SCSI standard is Ultra-2, which uses a 40 MHz clock rate to maximize data transfer rates to 80 Mbps. However, the latest SCSI standard is Ultra-3, which increases the maximum burst rate from 80 Mbps to 160 Mbps by utilizing a full clock rate rather than the half-clock rate of Ultra-2.
Data detection on an SCSI bus poses a special set of problems. In prior art systems, data detection on a SCSI bus is accomplished by sampling the bus at a particular clock rate to determine a change in one or more signals on the SCSI bus. If a change is detected, the sample containing the change is stored in a trace buffer along with a time stamp.
FIG. 1
depicts this prior technique for detecting data on the SCSI bus
100
. An SCSI data phase cycle
102
along with a first sample
104
and a second sample
106
, defining an analyzer sampling period
108
, are depicted with reference to FIG.
1
. At the time when the first sampling
104
is taken, the handshaking line
110
is inactive. However, by at the time the second sampling
106
is taken, the handshaking line
110
is active. Data is correctly detected on the SCSI bus because the status of the handshake line
110
differs during the analyzer sampling period
108
and the second sample also contains valid SCSI bus data associated with the transition of the handshake line
110
.
As depicted in
FIG. 2
, implementation of Ultra SCSI, specifically the transfer rate required, necessitates shortened setup and hold times relative to the handshake line
110
edge. Applying the prior art data detection technique described above, the second sample would be saved in the trace buffer because the status of the handshake line
110
differs during the analyzer sampling period
108
. Yet, in this case, the data that is saved as part of the second sample is not valid because the data hold time
112
has expired. For example, the data transfer rate in SCSI Ultra-2 at the protocol chip requires a minimum setup and hold time of 4.5 ns and 4.5 ns, respectively, and the requirements are longer for slower data transfer rates. However, in the SCSI Ultra-3, double transition clocking is used requiring data setup and hold times of 1.25 ns, resulting in a much smaller window for sampling data from the bus. The real window for capturing data in the protocol chip is actually smaller, because there are factors which affect and reduce the sampling window. Some of these factors include driver skew, approximately about 100 ps, and the signal rising and the signal falling edge differences, approximately about 200 ps. Therefore, the actual setup and hold time at the protocol chip is less than 1 ns.
Furthermore, in an SCSI system, there may be noise, which is induced by any electrical interference, crosstalk, reflections, or other sources. This interference influences the control signals on the SCSI bus, such as REQ or ACK signals. The receiver must have the means to select and detect the correct data in the right window at the right time. Prior art techniques for selection and detection of data include signal filter designs such as traditional glitch filters
120
. Unfortunately, the prior art filter design have several disadvantages as depicted in FIG.
3
. First, the active edge
122
of the control signal
124
is delayed by a programmable period of time t
126
. Also, the signal filters
120
do not take the first edge
128
of the ACK/REQ input signal
124
. The pulse width of noises to be filtered are also limited within the range of ≦t
126
. In addition, invalid data is potentially captured if a noise pulse width is larger than t
126
. The prior art filter designs are also process dependent.
Recent glitch filter designs
120
, for example as described in U.S. Pat. No. 5,563,532 ('532 patent), filter noise from both the falling edge
122
or rising edge
130
of the ACK/REQ input signals. The filter technique described in the '532 patent allows data detection from a bus utilizing dual edge data transfers or double transition clocking. However, as depicted in
FIG. 3
, the filter delays the falling
122
or rising edge
130
in an output filter signal
132
based on the duration of the shoulder or ringing noise
126
on the transition line of the ACK/REQ input signal
124
. If the delay
126
in the rising or falling edge of the output filter signal
132
is greater than the 1.25 ns setup and hold time required for SCSI Ultra-3, incorrect data is latched from the SCSI bus. The data cell
134
on the falling edge
122
and data cell
136
on the rising edge
130
will not be latched correctly.
What is needed is a data detection technique that filters noise from the transmission line without adding signal delay to a filtered output signal. A need also exists for technique that only takes the first edge of the asynchronous input signal for its filtered output signal. Data is then latched from the bus at the first edge of an ACK/REQ input signal, thereby eliminating all transmission noise that causes a shoulder or ringing noise on the transmission line. A need also exists for a technique that eliminates all noise inside a protection time window after the first edge the ACK/REQ input signal. A need for a protection time window that is programmable for faster or slower input frequencies also exists. The data detection circuitry must also be process independent, since no delay lines or cells are used.
SUMMARY OF THE INVENTION
The present invention overcomes the identified problems by providing a method and apparatus for data detection from a bus utilizing double transition clocking data transfers. More particularly, the present invention relates to a method and apparatus for detecting data on an SCSI bus as defined in the SCSI Ultra-3 specification. SCSI Ultra-3 protocol utilizes double-transition clocking. In double transition clocking, both the rising edge and falling edge of REQ (or ACK) signals are used to detect data. The invention, therefore, has two different circuits, one for the rising and one for the falling edge. A qualified asynchronous edge detector negative (QAEDN) detects a falling edge of an input ACK/REQ signal, and a qualified asynchronous edge detector positive (QAEDP) detects a rising edge of the input ACK/REQ signal.
In accordance with one embodiment of the invention, a method for data detection on the SCSI bus is disclosed in which a signal transition of an input signal is detected. When a falling edge of the input signal is detected, a rising edge in a negative edge signal is generated. When a rising edge of the input signal is detected, a rising edge in a positive edge signal is generated. A data cell is then latched from the SCSI bus in response to the rising edge of the positive
egative edge signal. A falling edge in the positive
egative edge signal is generated a after a predetermined clock period of time. The aforementioned steps are repeated for each detected signal transition of the input signal.
In accordance with another embodiment of the invention, an apparatus and system implementing the inventive methods is disclosed. A data detection apparatus includes a first qualified asynchronous edge detector negative configure
Cesari Kirk A.
Corrielus Jean B.
Seagate Technology LLC
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