Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1998-08-11
2001-07-24
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S762000, C257S763000, C438S623000, C438S624000, C438S643000, C438S644000
Reexamination Certificate
active
06265779
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to metal/insulator interconnect structures found in Very Large Scale Integrated (VLSI)and Ultra Large Scale Integrated (ULSI) circuits and packaging, and more particularly to interconnect structures comprising fluorine-containing low-k dielectrics and capping and/or liner materials selected to prevent reliability problems associated with out-diffusion of fluorine from the low-k dielectric into other parts of the structure.
BACKGROUND OF THE INVENTION
Device interconnections in Very Large Scale Integrated (VLSI) circuits or Ultra-Large Scale Integrated (ULSI) circuits or semiconductor chips are typically effected by multilevel interconnect structures containing patterns of metal wiring layers called traces. Wiring structures within a given trace or level of wiring are separated by an intralevel dielectric, while the individual wiring levels are separated from each other by layers of an interlevel dielectric. Conductive vias are formed in the interlevel dielectric to provide interlevel contacts between the wiring traces.
By means of their effects on signal propagation delays, the materials and layout of these interconnect structures can substantially impact circuit speed, and thus circuit performance. Signal propagation delays are due to RC time constants wherein R is the resistance of the on-chip wiring, and C is the effective capacitance between the signal lines and the surrounding conductors in the multilevel interconnection stack. RC time constants are reduced by lowering the specific resistance of the wiring material, and by using interlevel and intralevel dielectrics (ILDs) with lower dielectric constants.
The low dielectric constants of fluorine-containing dielectrics such as fluorinated diamond-like-carbon (FDLC) and fluorinated silicon glass (FSG) make them potentially useful as ILD materials in high performance VLSI and ULSI chips where interconnect wiring capacitance must be minimized. This use for FDLC is discussed by S. A. Cohen et al. in U.S. Pat. No. 5,559,367, entitled “Diamond-like carbon for use in VLSI and ULSI interconnect systems.” FDLC films can be fabricated by a variety of methods including sputtering, ion beam sputtering, and dc or rf plasma assisted chemical vapor deposition with a variety of carbon-bearing source materials, as described for non-fluorinated DLC films by A. Grill and B. S. Meyerson, “Development and Status of Diamond-like Carbon,” Chapter 5, in Synthetic Diamond: Emerging CVD Science and Technology, editors K. E. Spear and J. P. Dismukes, John Wiley and Sons, New York 1994, and F. D. Bailey et al. in U.S. Pat. No. 5,470,661 which issued Nov. 28, 1995. However, fluorine-containing ILDs such as FDLC cannot be integrated into these interconnect structures without taking suitable precautions such as capping layers to prevent fluorine in the FDLC from reacting with other materials in the interconnect structure during required processing steps at elevated temperatures above 300° C. While ILDs with reduced fluorine content would be expected to have smaller amounts of fluorine available to react with other materials, lower fluorine-content ILDs typically also have undesirably higher k values.
Capping materials such as the insulators silicon oxide and silicon nitride, and the conductive material TaN have been previously described for use with non-fluorine containing ILDs as (i) diffusion barriers (to prevent atoms of wiring material from diffusing into the ILD from where they may readily diffuse into active device regions), (ii) etch stop and permanent masking materials, and (iii) adhesion layers.
However, these conventional capping materials are not compatible with FDLC as indicated by capping material delamination and cracking in layered Si/FDLC (1000 nm) cap samples after a 350° C. anneal in He for 4 hours. Poor adhesion, delamination, and even cracking were present in samples where the FDLC had been given a “stabilization” anneal of 400° C. in He for 4 hours prior to capping.
Prior art utilization of capping materials such as silicon oxide, silicon nitride, and TaN in multilayer interconnect structures is illustrated in
FIGS. 1
,
2
,
3
A and
3
B.
FIG. 1
shows a schematic cross section view of a generic, 2-wiring-level interconnect structure
10
. Interconnect structure
10
comprises substrate
20
, conductive device contacts
30
in a first dielectric
40
, a first and second level of conductive wiring (
50
,
60
), and two layers of conductive vias (
70
,
80
) embedded in layers of a second dielectric
90
. Conductive wiring layers (
50
,
60
) and vias (
70
,
80
) are typically low-resistivity metals, for example, Al, Al alloyed with Cu or other elements, Cu, Cu alloys, or any of these materials, alone or in combination, doped with dopants, additives or impurities selected to improve electromigration properties. Contacts to packaging dies are provided by conductive contact pads
100
in a third dielectric
110
and insulating environmental isolation layer
120
. Interconnect structure
10
incorporates three capping materials: a conductive capping or liner material
130
lining the sidewalls and bottom surfaces of the conductive wiring and vias, an insulating capping material layer
140
overlying each wiring level over those areas not contacted by an overlying via, and an optional insulating capping layer
150
over some or all (shown) of each layer of dielectric
90
. Conductive liner or capping material
130
acts to provide adhesion and prevent metal diffusion into dielectric
90
; its conductivity provides electrical redundancy, and allows it to remain in the contact regions between conductive features in different levels. Insulating capping material
140
primarily serves to prevent metal diffusion into the overlying dielectric layers, but prevents other potentially undesirable interactions as well. Insulating capping material
150
is optionally left in the structure after use as an etch mask, etch stop, and/or polish stop during interconnect structure fabrication.
Interconnect structure
10
of
FIG. 1
would typically be fabricated by Damascene processing in which layers of dielectric are sequentially deposited, patterned to form cavities corresponding to the pattern of conductive material desired, overfilled with the conductive material, and then planarized to remove conductive material above the dielectric. This process is repeated as necessary for each additional layer.
Interconnect structures may also be fabricated by Dual Damascene processing, in which approximately double thicknesses of second dielectric material
90
are patterned with dual relief cavities corresponding to the pattern of a wiring level and its underlying via level.
FIG. 2
shows a schematic cross section view of a prior art 2-wiring-level interconnect structure
160
analogous to interconnect structure
10
in
FIG. 1
, except that the disposition of the capping materials
130
and
150
reflects the Dual Damascene method of processing. For example, since wiring level
60
and its underlying via level
80
are filled with conductive material in the same deposition step, there is no conductive cap material
130
between
50
and
70
, a characteristic distinguishing feature of all Dual Damascene processed interconnect structures.
FIGS. 3A and 3B
show two other Dual Damascene processed interconnect structures similar to interconnect structure
160
of
FIG. 2
, but different in the presence of insulating cap layer
170
, used as an etch stop to facilitate the patterning of the dual relief cavities in the double (via plus wiring level) layers of the second dielectric material
90
. In interconnect structure
180
in
FIG. 3A
, exposed regions of etch stop layer
170
are not removed before filling the dual relief cavities with conductive material; in interconnect structure
190
in
FIG. 3B
, exposed regions of etch stop layer
170
are removed before filling the dual relief cavities with conductive material.
While the interconnect structures
10
,
160
,
180
and
190
show two wiring levels, th
Grill Alfred
Jahnes Christopher Vincent
Patel Vishnubhai Vitthalbhai
Saenger Katherine Lynn
Chaudhuri Olik
Doan Theresa
International Business Machines - Corporation
Trepp Robert M.
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