Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure – With non-planar semiconductor surface
Reexamination Certificate
1998-10-05
2001-08-07
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Bipolar transistor structure
With non-planar semiconductor surface
C257S566000, C257S587000, C257S588000
Reexamination Certificate
active
06271575
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices on semiconductor substrates, and more particularly relates to a method for making bipolar and MOS devices using variations in the punchthrough and field oxide (FOX) thickness formed by the LOCal Oxidation of Silicon (LOCOS) method. The multiple thickness of the LOCOS is used as a self-aligning implant mask, and to electrically isolate the device areas. This eliminates the multiphotoresist masking steps for ion implantation and the accompanying alignment tolerance limitations, thereby providing high device-packing density and a cost-effective manufacturing process.
(2) Description of the Prior Art
Typically the fabrication of bipolar and MOS transistors requires a considerable number of processing steps. Because of their vertical structure, bipolar transistors require a series of separate implant masks and ion implant steps for making the emitter, base, and collector This is because the bipolar requires multiple masking and implant steps to form the collector, base, and emitter at different depths in the silicon substrate. On the other hand, the FETs, such as used on dynamic random access memory (DRAM) circuits are basically surface devices that are simpler to fabricate, and can have improved device characteristics by including a doped shield region under the FET source, which can increase driver current and increase breakdown voltage between source and drain. However, an additional masking step is required to implant the shield region under the FET source. Therefore, it is desirable to be able to fabricate the bipolar and/or field effect transistors with reduced complexity. It is also desirable to provide a single self-aligning implant mask to decrease device size and to increase device-packing density, which would not be achieved otherwise by the conventional method in which separate lithographic masking and alignment tolerances limit device size.
One method of using a screen oxide layer having various thicknesses to form devices at various depths in the substrate is described by Joyner, U.S. Pat. Nos. 5,364,800 and 5,548,149. Joyner teaches a method of patterning a screen oxide implant layer having different thickness which he then uses to implant oxygen to form silicon-on-insulator (SOI) substrates having silicon device areas of various depths.
Therefore, there is still a strong need in the semiconductor industry to make circuits with improved self-aligned semiconductor devices for improved density and circuit performance while reducing manufacturing cost.
SUMMARY OF THE INVENTION
It is therefore a principal object of this invention to form a self-aligned ion implantation mask for semiconductor devices using a novel LOCOS method.
It is another object of this invention to use this novel LOCOS method to make a self-aligned multiple thickness silicon oxide ion implant mask for forming bipolar transistors and/or FETs, while forming the field oxide isolation, and therefore reducing the number of photoresist ion implant masking steps.
A further object of this invention is to provide a self-aligned multiple thickness ion implant mask that also reduces the size of the devices resulting in higher circuit density and improved circuit performance.
It is also an object of this invention to form bipolar and FET transistors using an array of silicon nitride stripes and the novel LOCOS method to make bipolar power transistors and FETs having variable sizes on the same substrate.
In accordance with the objects of the invention, a novel LOCOS method is used to fabricate bipolar and/or field effect transistors by forming a self-aligned silicon oxide implant mask. The oxide implant mask is formed having a different oxide thickness over each region of the bipolar, such as base, collector, and emitter, and for FET devices over the source and gate/drain regions. This eliminates the need for multiple photoresist masking steps as used in the conventional method. The silicon oxide mask also remains on the substrate to serve as part of the structure and to electrically insulate the silicon devices from the next level of electrical interconnections.
These bipolar transistors or FETs are built in and on a single-crystal semiconductor substrate that is doped with a P-type dopant, such as boron. However, silicon substrates having doped P- and N-wells can also be used to make CMOS devices for fabricating BiCMOS circuits. The method utilizes both a single silicon nitride stripe having varying well defined widths to make an oxidation barrier mask for making submicrometer bipolar transistors, and an array of silicon nitride stripes having various well defined widths and spacings on the silicon substrate for making larger power transistors. Continuing with the process, a thermal oxidation is carried out to form a field oxide (FOX) around the silicon nitride stripes, while this thermal oxidation also laterally oxidizes the silicon substrate under the silicon nitride stripes (mask) to form the ion implant mask of various thicknesses. The lateral oxidation is commonly referred to as the punchthrough oxide when it extends completely under the silicon nitride stripes.
This novel LOCOS method and resulting structure starts by forming a pad oxide layer on the silicon substrate surface by thermal oxidation. A chemical vapor deposited (CVD) silicon nitride layer is deposited on the pad oxide layer to provide an oxidation barrier layer when the thermal oxidation is later carried out to form the field oxide (FOX). The silicon nitride layer is then patterned using photolithographic techniques and anisotropic plasma etching to form a single silicon nitride stripe over each device area having varying decreasing widths for emitter, base, and collector regions, respectively, for the bipolar transistors. The silicon nitride layer can also be patterned over other device areas for FETs having silicon nitride stripes of decreasing widths. A wide silicon nitride area is formed over the FET source area to prevent punchthrough oxide from forming, while a silicon nitride stripe having a narrower width is formed over the gate electrode/drain area to provide a punchthrough oxide mask, as an implant block-out mask, over the gate electrode/drain area.
The silicon substrate is then thermally oxidized to form the field oxide isolation around the device areas that have the silicon nitride stripes, and concurrently and laterally oxidizes the substrate under the silicon nitride stripes to form the punchthrough oxide which later serves as a self-aligned oxide implant mask. For the bipolar transistors, the oxide implant mask over the collector resulting from the punchthrough oxidation is thinner than the field oxide region, while the oxide implant mask over the base region is thinner than the oxide implant mask over the collector region. And further, the width of the silicon nitride stripe over the emitter region is made sufficiently wide to prevent the punchthrough oxide from forming, thereby retaining the thin pad oxide which was previously grown over the emitter region. The silicon nitride mask is then removed by wet etching to provide a self-aligned oxide implant mask having different thicknesses over the collector, base, and emitter regions, and also different thicknesses over the source and gate/drain regions of the FET. A first photoresist implant block-out mask is used to protect the FET device areas from implant while a series of consecutive ion implants is carried out to form the collector, base, and emitter for the bipolar transistors. This eliminates the need for a series of separate photoresist implant masks that is required in the prior art. However, if only one type of device (bipolar or FET) is desired, the photoresist implant block-out masks are not required and the process complexity is reduced.
The collector ion implant energy is sufficient to provide a projected range R
p
(C) that is greater than the oxide implant mask over the collector regions so as to form a collector contact in the sili
Chartered Semiconductor Manufacturing Ltd.
Hu Shouxiang
Pike Rosemary L. S.
Saile George O.
Thomas Tom
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