Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-07-27
2002-12-17
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180, C365S185300
Reexamination Certificate
active
06496417
ABSTRACT:
BACKGROUND OF THE INVENTION.
1. Field of Invention
This invention relates to floating gate memory devices, such as flash memory, and in particular to methods and circuits for repairing over-erased floating gate memory cells.
2. Description of Related Art
Non-volatile memory design based on integrated circuit technology represents an expanding field. Several popular classes of non-volatile memory are based on arrays of floating gate memory transistors that are electrically erasable and programmable.
The act of programming a memory array of floating gate memory transistors in one popular approach involves injecting the floating gate of addressed cells with electrons which causes a negative charge to accumulate in the floating gate and the turn-on threshold of the memory cell to increase. Thus, when programmed, the cells will not turn on, that is, they will remain non-conductive when addressed with read potentials applied to the control gates. The act of erasing a cell having a negatively charged floating gate involves removing electrons from the floating gate to lower the threshold. With the lower threshold, the cell will turn on to a conductive state when addressed with a read potential to the control gate. For an opposite polarity array, programming involves selectively removing electrons from the addressed cells' floating gates.
Floating gate memory cells suffer the problem of over-erasure, particularly when erasing involves lowering the threshold by removing electrons from the floating gate. During the erase step, over-erasure occurs if too many electrons are removed from the floating gate leaving a slight positive charge. The positive charge biases the memory cell slightly on, so that a small current may leak through the memory even when it is not addressed. A number of over-erased cells along a given data line can cause an accumulation of leakage current sufficient to cause a false reading.
In addition to causing false readings, when floating gate cells are over-erased, it makes it difficult to successfully reprogram the cells using hot electron programming, particularly with embedded algorithms in the integrated circuits. This difficulty arises because the program current will be large and, due to series resistance, the effective V
DS
across cell will drop so that the electron injection efficiency will decrease.
Further, because the erase and program operations can affect different cells in a single array differently, floating gate memory designs often include circuitry for verifying the success of the erasing and programming steps. See, for instance, U.S. Pat. No. 4,875,118, entitled VOLTAGE MARGINING CIRCUIT FOR FLASH MEMORY, invented by Jungroth. If the array does not pass erase verify, the entire array is usually re-erased. The re-erase process can aggravate over-erased cells in the array.
One solution to the over-erase problem associated with the erase verification process is disclosed in U.S. Pat. No. 5,414,664, FLASH MEMORY WITH BLOCK ERASE FLAGS FOR OVER-ERASURE PROTECTION, issued to Lin et al. on May 9, 1995, which shows a method and a device where only those blocks which fail the erase verify operation are re-erased. Accordingly, a re-erase of the entire array after each verify operation is not required. This mitigates the over-erase phenomenon, but does not solve it entirely.
Thus, a repair process has been developed to correct over-erased cells. U.S. Pat. No. 5,233,562, entitled METHODS OF REPAIRING FIELD-EFFECT CELLS IN AN ELECTRICALLY ERASABLE AND ELECTRICALLY PROGRAMMABLE MEMORY DEVICE, issued to Ong, et al., describes processes for such repair using so-called drain disturb, source disturb or gate disturb techniques. After each repair in the Ong patent, a time-consuming repair verification operation of the entire array is provided. See, also, U.S. Pat. No. 5,416,738 to Shrivastava for further background information.
Another attempt to solve the over-erase problem is described in U.S. Pat. No. 5,546,340, entitled NON-VOLATILE MEMORY ARRAY WITH OVER-ERASE CORRECTION, issued to Hu et. al. Hu describes a negatively biased substrate. Hu describes bulk correction of over-erased devices within an array. Hu describes bulk correction of an array of over-erased devices as carried forth in a convergence technique which utilizes higher floating gate injection currents.
A low current method of programming flash EEPROMS is described in U.S. Pat. No. 5,487,033, entitled STRUCTURE AND METHOD FOR LOW CURRENT PROGRAMMING OF FLASH EEPROMS, issued to Keeney et. al. Keeney indicates that a control gate voltage may be stepped or ramped from a minimum value to a maximum value to further reduce the peak channel current and to allow the flash cell threshold voltage to be placed to an exact value, for Multilevel Flash EEPROM cell applications.
For further discussion of a technique for correction of over-erasure of flash EPROM's, please refer to U.S. Pat. No. 5,467,306, entitled METHOD OF USING SOURCE BIAS TO INCREASE THRESHOLD VOLTAGES AND/OR TO CORRECT FOR OVER-ERASURE OF FLASH EPROM's, issued to Kaya, et. al.
For many repair processes in the prior art, soft programs are implemented as bulk operations applied to all erased cells in a particular memory at the same time. Such bulk operation soft programs consume currents that are excessive for low power applications.
Another problem arises during repair (or soft program) processing after the erase cycle because the soft program cycle is applied to all of the erased cells at the same time, without regard to whether a particular bit line has one or more cells that have been over-erased to a defective condition. Defectively over-erased cells can have extremely low threshold voltages after several erase cycles. Bit lines containing such low threshold voltage cells are considered defective because they consume extremely high current during soft programming. Pumping circuits can be used to provide the data line voltage in a soft program cycle. Because of the limited current capability of such pumping circuits, the inefficiencies caused by the loss of current to over-erased cells are exacerbated when the data line voltage is provided by a pumping circuit.
In any case, the repair and repair verification processes are time-consuming.
Therefore, a method and device which repairs over-erased cells in FLASH memory, and other floating gate memory, more quickly and efficiently is needed.
SUMMARY OF THE INVENTION
One aspect of the invention provides a method for soft programming successive bit lines in an integrated circuit having floating gate memory cell arrays. The soft programming method is adapted to quickly and efficiently repair over-erased cells. The soft programming is suitable use in an embedded erase algorithm of other erase sequences for integrated circuit flash memory devices and for other floating gate memories disposed in integrated circuits. According to the invention, the soft program voltage is applied, on a bit line by bit line basis, to successive subject bit lines within an integrated circuit memory array. The bit line soft programming method is also referred to herein as the BLISP method.
The BLISP method is accomplished in a floating gate integrated circuit. The integrated circuit includes a first memory array having a plurality of bit lines. The bit lines correspond to floating gate memory cells. The memory cells are configured to be programmed and erased. Each of the cells has a drain, a source, and a control gate. The control gates of the cells are in communication with word lines.
The BLISP method includes maintaining the word lines at a predetermined word line voltage level. The method also includes generating a soft programming pulse having a soft programming voltage level, selecting a selected bit line, and during the maintaining, applying the soft programming voltage level to cells disposed on a subject bit line corresponding to the selected bit line. This basic BLISP method is typically used for memory arrays with zero defective bit lines, in which case, the subject bit line comprises the selected bi
Chang Tso-Ming
Chen Han Sung
Lin Yu-Shen
Lu Wen-Pin
Shiau Tzeng-Huei
Haynes Mark A.
Haynes Beffel & Wolfeld LLP
Macronix International Co. Ltd.
Zarabian A.
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