Method and integrated circuit apparatus for reducing...

Details Method and integrated circuit apparatus for reducing... Method and integrated circuit apparatus for reducing...

2007-04-17

2007-04-17

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S293000

Reexamination Certificate

active

10963532

ABSTRACT:
Provided are a method and apparatus for reducing the number of power ports equipped with an integrated circuit (IC) apparatus by reducing the number of bus outputs that are simultaneously switched, with the use of a master clock signal and a slave clock signal, which is a variation of the master clock signal. The IC apparatus includes a slave clock signal generator, which receives the master clock signal and generates a slave clock signal for controlling simultaneously switching outputs; and a flipflop circuit, which transmits a signal to an external device in synchronization with the slave clock signal.

REFERENCES:
patent: 6943610 (2005-09-01), Saint-Laurent
patent: 7003060 (2006-02-01), Naka et al.
patent: 7010072 (2006-03-01), Lee et al.
patent: 60-117819 (1985-06-01), None
patent: 61-008786 (1986-01-01), None
patent: 04-252518 (1992-09-01), None
patent: 06-311000 (1994-11-01), None
patent: 07-022594 (1995-01-01), None

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