Method and electronic circuit for signal processing, in...

Details Method and electronic circuit for signal processing, in... Method and electronic circuit for signal processing, in...

1999-02-16

2001-08-28

Mai, Tan V. (Department: 2121)

Electrical computers: arithmetic processing and calculating

Electrical analog calculating computer

Particular function performed

C708S835000

Reexamination Certificate

active

06282559

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the priority of Swiss patent application 375/98, filed Feb. 17, 1998, the disclosure of which is incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION
The invention relates to a method and a circuit for the calculation of at least one discrete probability distribution.
Many signal processing algorithms consist essentially of elementary sum-product computations with quantities that are (or can be viewed as representing) probability distributions.
It is therefore an object of the present invention to implement these elementary computations by means of simple electronic circuits.
BRIEF SUMMARY OF THE INVENTION
Now, in order to implement these and still further objects of the invention, which will become more readily apparent as the description proceeds, the invention manifested by a method for the calculation of at least one discrete probability distribution [p(Z
1
), . . . , p(z
k
)], k≧2, from discrete probability distributions [p(x
1
), . . . , p(x
m
)], m≧2, and [p(y
1
), . . . , p(y
n
)], n≧2, according to the formula p(z)=&ggr;&Sgr;
x
&Sgr;
y
p(x)p(y)f(x, y, z) with at least one given {0,1}-valued function f(x, y, z) and with a scaling factor &ggr; by means of an electronic circuit, wherein said electronic circuit comprises a first and a second circuit section, the first circuit section comprising m current inputs (I
x,1
. . . I
x,m
) for [p(x
1
), . . . , p (x
m
) ] and n current inputs (I
y,1
. . . I
y,n
) for [p(y
1
) , . . . , p(y
n
)], m·n transistors T
i,j
, i=1 . . . m, j=1 . . . n, wherein an emitter or a source of transistor T
i,j
is connected to the current input for p(x
i
) and a base or a gate of transistor T
i,j
is connected to the current input for p(y
j
), additional n transistors T
j
, j=1 . . . n, wherein a base or gate and a collector or drain of transistor T
i
is connected to the current input for p(y
j
) and an emitter or source is connected to a reference voltage; wherein the second circuit section comprises k current outputs for [P(z
1
), . . . , p(z
k
)]; said method comprising the steps of summing the collector or drain currents of said transistors T
i,j
corresponding to the required product terms p(x
i
)p(y
j
) and copying those currents that correspond to multiply used product terms.
In another aspect of the invention, the invention relates to a circuit for signal processing comprising several circuit sections, each circuit section having m inputs x
1
, . . . , x
m
and n inputs y
1
, . . . , y
n
, m≧2, n≧2 and m·n transistors T
i,j
, i=1 . . . m, j=1 . . . n, wherein the emitter or source of transistor T
i, j
is connected to the input x
i
and the base or gate of transistor T
i,j
is connected to input y
i
, wherein each circuit section further comprises n transistors T
j
, j=1 . . . n, wherein the base or gate and the collector or drain of transistor T
j
is connected to the current input for p(y
j
) and the emitter or source is connected to a fixed reference voltage; wherein m, n and k can be different for differing circuit sections, wherein several circuit sections are connected in such a way that the inputs x
1
, . . . , x
m
or y
1
, . . . , y
n
of one circuit section are connected to the collector or drain of the transistors T
i,j
of another circuit section according a connection pattern, wherein an input x
i
or y
j
can be connected to several transistors T
i,j
of the other circuit section, and wherein such connection is implemented directly or via current mirrors and/or vector scaling circuits and/or switches and/or delay elements, and wherein the circuit comprises at least two differing circuit sections and/or at least two differing connection patterns between circuit sections.
In yet another aspect, the invention relates to a method for the calculation of at least one discrete probability distribution [p(z
1
), . . . , p(z
k
)], k≧2, from discrete probability distributions [p(x
1
), . . . , p(x
m
)], m≧2, and [p(y
1
), . . . , p(y
n
)], n≧2, according to the formula p (z)=&ggr;&Sgr;
x
&Sgr;
y
p(x)p(y)f(x, y, z) with at least one given {0,1}-valued function f(x, y, z) and with a scaling factor &ggr; by means of an electronic circuit, wherein said electronic circuit comprises a first and a second circuit section, the first circuit section comprising m current inputs (I
x,1
. . . I
x,m
) for [p(x
1
), . . . , p(x
m
)] and n current inputs (I
y,1
. . . I
y,n
) for [p(y
1
), . . . , p(y
n
)], m·n transistors T
i,j
, i=1 . . . m, j=1 . . . n, wherein an emitter or a source of transistor T
i,j
is connected to the current input for p(x
i
) and a base or a gate of transistor T
i,j
is connected to the current input for p(y
j
), additional n transistors T
j
, j=1 . . . n, wherein a base or gate and a collector or drain of transistor T
i
is connected to the current input for p(y
j
) and an emitter or source is connected to a reference voltage; wherein the second circuit section comprises k current outputs for [p(z
1
), . . . , p(z
k
)]; said method comprising the steps of summing the collector or drain currents of said transistors T
i,j
corresponding to the required product terms p(x
i
)p(y
j
), copying those currents that correspond to multiply used product terms and using said method for calculating a problem selected from the group of separating interfering digital signals; separating users in multi-access communication systems; equalization of digital data; combined equalization, user separation and decoding of coded, digital signals; calculating at least some metric vectors in a sum product algorithm; decoding an error correcting code; decoding encoded data; source coding; carrying out a forward-backward algorithm in a hidden Markov model; and carrying out probability propagation in a Bayesian network.
The method according to the invention exploits the fact that the described circuit is topologically closely related to the mathematical structure of the probability distribution that is to be computed and that it can easily be combined with further circuits to form larger networks.
The transistors in the claimed circuits may not only be FET or bipolar transistors, but also “super transistors” including, e.g., Darlington transistors or cascodes.
If several discrete probability distributions corresponding to several {0,1}-valued functions are to be calculated from the same input values, all product terms are preferably calculated only once in the first circuit section, wherein the different sums for the individual functions are calculated in the second circuit section. Currents of multiply used product terms can e.g. be copied in current mirrors.
The circuit according to the present invention may comprise several circuit sections that are combined according to some connection patterns. By a suitable choice of the circuit sections and of the connection patterns, various complex signal processing tasks can be carried out. For assessing equality of such connection patterns, any intermediate current mirrors or any vector scaling circuits between the sub-circuits are to be disregarded.
Due to its topological simplicity and its scalability, the circuit technology of the present invention allows highly efficient implementation.
The invention is particularly suited to the computation of metric vectors in a sum-product algorithm, to the decoding of error correcting codes or coded modulation schemes, and to further tasks that are mentioned below.


REFERENCES:
patent: 4374335 (1983-02-01), Fukahori et al.
patent: 5059814 (1991-10-01), Mead et al.
patent: 5764559 (1998-06-01), Kimura
patent: 6058411 (2000-05-01), Boltunov
patent: 19725275 A1 (1998-12-01), None
patent: 1024450 A1 (2000-08-01), None
Bahl, L.R. et al., IEEE Transactions on Information Theory, pp 284-287, US IEEE, New York, Mar. 1974.
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