Method and device to execute two instruction sequences in an ord

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3642628, 364263, 3642631, 3642394, G06F 930

Patent

active

049567705

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention relates to a method and a device for executed two instruction sequences in an order determined in advance, the executions including selection of read instructions each containing a read address for retrieval of data information stored in one of a plurality of main memory locations accessible by their individual adresses, as well as selection of write instructions each containing a write address and data information, for transferring this data information to a main memory location accessible by this write address and wherein the data information used in conjunction with the execution of the sequence which is second according to determined order, not being guaranteed in advance to be independent of the data information obtained in conjunction with the execution of the sequence which is first according to the determined order.


BACKGROUND ART

A trivial, conventional solution of the above mentioned information handling problem resides in that the execution of the second sequence is not started until the execution of the first sequence is terminated. This trivial solution is obtained as a natural necessity in a data processing system controlled by a single processor such that the sequences are executed one at a time using main memory locations common to both sequences.
It is known to increase data processing capacity by parallel execution of the instruction sequences. As long as the sequences are guaranteed in advance to be mutually independent, fault-free parallel operation is achieved with the aid of so-called pre-processing or multi-processing, or also with the aid of a one-processor system which includes at least two data processing units, each of which executes its instruction sequence. It is known to realize information handling both by means of a main memory which is common to a plurality of data processing units and by means of a plurality of separate memories each associated with its data processing unit and mutually updated from time to time.
When there are sensitive instruction sequences which affect each other, and which must therefore be executed in a prescribed order, e.g., according to the journal Computer Design, Aug. 15, 1985, pp 76-81, or "Balance 8000 System Technical Summary, Sequent Computer Systems, Inc", programming languages, compilers and sequence hardware for parallel processing of mutually independent sequences, are used while parallel processing of the sensitive sequences is prevented.


SUMMARY OF THE INVENTION

As already mentioned in the introduction, the present invention relates to data information processing while using a main memory common to both sequences. In the proposed information processing, both sequences are executed in parallel without having to take notice of the predetermined order of execution. To ensure the predetermined order it is, however, necessary to prevent data information obtained from selected write instructions associated with the second sequence from being transferred to the main memory locations during the preceding execution of the first sequence. The dependence of the second sequence on the first sequence is monitored and the prescribed order is achieved with the aid of an intermediate storage unit which includes an auxiliary memory and comparison circuits.
Addresses obtained due to read instructions selected during execution of the second sequence are intermediately stored in the auxiliary memory. Every write address selected during the execution of the first sequence is compared with each of the read addresses stored in the auxiliary memory. As long as no addresses are determined to be the same, no data information dependent on data information obtained during the execution of the first sequence is used during the execution of the second sequence. If during execution of the second sequence information is retrieved from a main memory location, and this information is then corrected due to a write operation associated with the first sequence, i.e., if the two sequences are no longer mutually independent, the a

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Granberg, "APZ 150: A Multiprocessor System for the Control of Transit Telephone Exchanges", Telefonakiebolaget, 1976, pp. 287-306.
Intel "APX 286 Hardware Reference Manual", vol. 2, pp. 1-3, vol. 3, pp. 56-57.
"Balance 8000 Technical Summary", Chapter 1-Introduction pp. 1-17, Dated Dec. 11, 1985.
"Backup Support Gives VME Bus Powerful Multi-Processing Architecture", Electronics, Mar. 22, 1984, pp. 132-138.
"Supercomputer Expands Parallel Processing Options", Computer Design, Aug. 15, 1985, pp. 76-81.

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