Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2002-07-11
2003-12-09
Wong, Don (Department: 2821)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C315S169300, C345S087000
Reexamination Certificate
active
06661395
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a system and method to drive a plasma display. In particular, the present invention relates to a plasma display driving system and a method of driving a plasma display, by changing scanning frequency, to reduce the scanning time during address period.
2. Description of the Related Art
An AC memory type plasma display panel (referred to as PDP hereafter) has many advantages such as small size, high display ability, and high reliability. Thus, the PDP can be found in various wide screen electronic devices for displaying output data. The current method of driving a plasma display panel is achieved through a plurality of subframe-display operations, which altogether constitute a full frame-display operation. For example, a picture frame in a plasma display panel with 256 gray levels may comprise eight subframes SF
0
~SF
7
as shown in FIG.
1
A. Each subframe-display operation comprises steps of resetting, scanning, and sustaining the display signal. Specifically, a plasma display panel is driven by a driving signal that comprises an erasing period, a addressing period, and a sustaining period. During the erasing period, residual ions of each illuminant cell of a PDP are erased using a voltage pulse having a pulse width shorter than a sustaining pulse. During the addressing period, external data are input using a voltage pulse having a voltage higher than a sustaining pulse of the erasing period. During the sustaining period, an AC voltage of a constant frequency is applied to avoid an ignition miss or incorrect display and to obtain a correct power margin.
FIG. 1B
shows a cross section of a conventional PDP structure, and
FIG. 1C
shows a schematic top view of the data and scanning electrodes of the same PDP. As shown in
FIG. 1B
, a PDP is constructed by joining a front glass substrate
1
with a rear glass substrate
2
, wherein data electrodes
3
for inputting external data are formed on the surface of the front glass substrate
1
that opposes the rear glass substrate
1
. Furthermore, a plurality of ribs
4
is defined on the data electrodes
3
to form illuminant cells. A plurality of sustaining electrodes
7
and scanning electrodes
8
in parallel direction, on the other hand, are formed on the surface of the rear glass substrate
2
that opposes the front glass substrate
1
, wherein the above-mentioned data electrodes
3
are formed perpendicular to both the sustaining electrodes
7
and the scanning electrodes
8
. In addition, the surfaces of both the sustaining electrodes
7
and scanning electrodes
8
are coated with a dielectric layer
6
(such as a MgO layer) for protecting the surfaces of the electrodes. Furthermore, a fluorescence material
5
(such as phosphorous) is deposited between ribs (where the illuminant cells reside) for illumination to occur as soon as a voltage is applied. As shown in
FIGS. 1C and 1D
, a typical conventional plasma display panel comprises a plurality of row plasma display units (represented by L
1
~LN). Each row display unit has one of the plurality sustaining electrodes
7
(represented by a corresponding X
1
~X
N
), one of the plurality of parallel scanning electrodes
8
(Y
1
~Y
N
); for example, the first row display unit L
1
comprises the first sustaining electrode X
1
, and the first scanning electrode Y
1
. The plurality of illuminant cells of the first row display unit L
1
is driven by the X
1
, Y
1
simultaneously during the sustaining period. The plurality of data electrodes
3
(D
1
~D
M
) are disposed perpendicular to both the sustaining electrodes
7
(X
1
~X
N
) and the scanning electrodes
8
(Y
1
~Y
N
). Each of the sustaining electrodes
7
(X
1
~X
N
) is connected to the others and thereby the electrodes can be driven synchronously. In contrast, each of the scanning electrodes
8
(Y
1
~Y
N
) is connected separately from the other electrodes so as to actuate each of the electrodes independently. Thus, external data are input to each illuminant cell of the plasma display panel via the data electrodes
3
(D
1
~D
M
) by controlling both the sustaining electrodes
7
(X
1
~X
N
) and the scanning electrodes
8
(Y
1
~Y
N
).
FIG. 2
is a driving signal diagram of various electrodes of the plasma display panel shown in
FIGS. 1B
,
1
C, and
1
D, which are driven according to the method of a prior art. Accordingly, a plasma display panel is driven by a driving signal that comprises an erasing period, an addressing period, and a sustaining period. During the erasing period, a very short pulse V
W
of a high voltage is applied to all of the sustaining electrodes
7
(including X
1
~X
N
), and all of the scanning electrodes
8
(including Y
1
~Y
N
) are connected to the ground V
g
, so as to remove the remaining residual ions. At this point, no data electrodes
3
(including D
1
~D
M
) are driven yet. During the addressing period, a bias V
K
is applied to all of the sustaining electrodes
7
(including X
1
~X
N
), so the scanning electrodes
8
(Y
1
~Y
N
) can input external data sequentially via the data electrodes
3
(D
1
~D
M
) based on an addressing signal V
Y
. At this point, the scanning electrodes
8
(Y
1
~Y
N
) are connected to a row address decoder (not shown in the figure) to receive an addressing signal, and the data electrodes
3
(D
1
~D
M
) are connected to external data to proceed writing operations. During the sustaining period, a periodic voltage pulse V
S
is alternately applied to the sustaining electrodes
7
(X
1
~X
N
) and the scanning electrodes
8
(including Y
1
~Y
N
) to maintain the luminance of the illuminant cells.
FIG. 3
shows the timing chart of the output pulse of the scanning electrodes Y
1
~Y
N
. In
FIG. 3
, the scanning frequency of each scanning electrode is f
p
.
As shown in
FIG. 2
, addressing cost most of the frame time. For a 600×400 256 color PDP as a example, if erasing period takes 150 us and each address line takes 3 us, then the erasing period and addressing period take 15.6 ms [(150+3×600)×8/1000=15.6], it is about 90% of one frame time(16.7 ms). Thus, the time for sustaining is too short to generate sufficient brightness.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a plasma display driving system and a method to drive a plasma display. When misfiring does not occur, the frequency, pulse width, and interval of the signals output by the scanning electrodes are modified to decrease the addressing period. Thus, the sustaining period is increased to raise the brightness of the PDP.
To achieve the above-mentioned object, the present invention provides a plasma display driving system including a controlling circuit, a scan driver, and a data driver. The controlling circuit outputs a first scan driving pulse and a second scan driving pulse, and a third scan driving pulse during the addressing period. The frequency of the first scan driving pulse is higher than the second scan driving pulse, and the frequency of the second scan driving pulse is higher than the third scan driving pulse. The scan driver drives the first scanning electrodes, the second scanning electrodes, and the third scanning electrodes according to the first scan driving pulse, the second scan driving pulse, and the third scan driving pulse respectively. The data driver drives the first data electrodes, the second data electrodes, and the third data electrodes responding to the first scanning electrodes, the second scanning electrodes and the third scanning electrodes when the scanning electrodes are driven.
REFERENCES:
patent: 6037920 (2000-03-01), Mizutome et al.
patent: 2001/0020923 (2001-09-01), Homma
patent: 2002/0063662 (2002-05-01), Nagakubo et al.
Ho Bing-Ming
Huang Jih-Fon
Lo Lih-Shang
AU Optronics Corp.
Ladas & Parry
Tran Chuc
Wong Don
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