Method and device to control a memory

Details Method and device to control a memory Method and device to control a memory

1995-02-07

1997-07-01

Beausoliel, Jr., Robert W.

Excavating

371 511, G01R 3128, G06F 1100

Patent

active

056447086

ABSTRACT:
A method and a device for determining that digital information written into a memory is correctly readable before such read information, in the form of a number of coordinated bit positions, is used to control one or several functions, where the functions can be activated by a computer unit. A selected address position or positions within the memory corresponding to the stored digital information points out a first set of bits, required to control and/or initiate the functions, and a second set of bits serving as a control sum. The second set of bits is calculated taking into consideration the current set of bits corresponding to the first set of bits and a third set of bits, corresponding to the address position currently selected for readout. When the following readout of the digital information out of the memory is performed, a new control sum is calculated in the same way, taking into consideration the currently read bit positions corresponding to the first set of bits and a fourth set of bits corresponding to the address position currently selected for readout, to form a fifth set of bits. The read digital information is accepted as correct when a comparison is performed and agreement is found between the second set of bits and the fifth set of bits.

REFERENCES:
patent: 3914741 (1975-10-01), Bonser
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patent: 4811347 (1989-03-01), Bolt
patent: 5321706 (1994-06-01), Holm
patent: 5337317 (1994-08-01), Takamisawa
patent: 5361252 (1994-11-01), Sallberg et al.
patent: 5392302 (1995-02-01), Kemp
patent: 5537425 (1996-07-01), Tsou
"Parity Mechanism for Detecting Both Address and Data Errors", J.D. Dixon et al., IBM Technical Disclosure Bulletin, vol. 24, No. 1B, Jun. 1981.

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