Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Patent
1997-07-18
1999-11-16
Lane, Jack A.
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
36518511, G11C 700
Patent
active
059869658
ABSTRACT:
A device for writing a data in a non-volatile memory circuit having a plurality of memory cells includes an input/output port inputting and outputting an address and the data, a first decoder decoding the address from the input/output port and outputting a first decoded data, a second decoder decoding the data from the input/output port, sequentially determining a block value corresponding to the address from the input/output port, and outputting a second decoded data, a data processing part receiving and processing the second decoded data from the second decoder and outputting an address bit value, a first DEMUX receiving the address bit value from the data processing part and outputting a demultiplexed data corresponding to the block value determined in the second decoder, a NOR gate part receiving the first decoded data from the first decoder and the demultiplexed data from the first DEMUX, and outputting a signal having a logical NOR result, a second DEMUX receiving an output signal from the data processing part and outputting a demultiplexed data, and read/write device receiving the demultiplexed data and writing the data in the plurality of memory cells.
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H. Onoda, et al., A Novel Cell Structure Suitable for A 3 Volt Operation, Sector Erase Flash Memory, 1992, IEEE Tech Dig. Of IEDM, P. 599-602.
R. Rofan, et al., Stress-Induced Oxide Leakage, 1991, IEEE EDL, vol. 12 No. 11, P. 632-634.
Lane Jack A.
LG Semicon Co. Ltd.
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