Method and device for the digital synthesis of a clock signal

Details Method and device for the digital synthesis of a clock signal Method and device for the digital synthesis of a clock signal

1988-06-27

1990-01-23

Griffin, Robert L.

Pulse or digital communications

Spread spectrum

Direct sequence

375118, 307262, H03D 324

Patent

active

048963380

ABSTRACT:
According to the method, the clock signal is obtained from a phase increment datum .DELTA.P, representing the frequency to be synthesized. It consists in performing a binary number M modulo addition of each phase increment with the modulo M sum of the phase increments already totalized inside a phase accumulating device. After each overflow of capacity of the accumulator device, the remaining residual phase error P.sub.K is read in the accumulating device. Correlatively, 2.sup.Q clock signals with a period T.sub.c, phase-shifted with respect to each other by T.sub.c /2.sup.Q are generated. A temporal error .DELTA.t.sub.K is computed by obtaining the ratio P.sub.K /.DELTA.P between the residual phase error P.sub.K and the phase increment .DELTA.P per period T.sub.c. Finally that clock signal for which the phase shift with respect to the computation clock signal is closest to the computed residual phase is selected. /

REFERENCES:
patent: 3638192 (1972-01-01), Rutherford et al.
patent: 3851101 (1974-11-01), En et al.
patent: 4492914 (1985-01-01), Hitomi
patent: 4493094 (1985-01-01), Thomson
patent: 4617679 (1986-10-01), Brooks
patent: 4740999 (1988-04-01), Wagner
IBM Technical Disclosure Bulletin, vol. 17, No. 10, Mars 1975, p. 2981, New York, U.S.; F. E. Stuebner: "Clock Pulse Generator With Adjustment For Cycle Length".
IBM Technical Disclosure Bulletin, vol. 10, No. 3, about 1967, p. 235, New York, U.S.; H. Deutsch et al.: "Digitally Programmable Derived Clock".

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