Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Patent
1996-04-01
1998-07-28
Karlsen, Ernest F.
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
371 225, G01R 3128
Patent
active
057867038
DESCRIPTION:
BRIEF SUMMARY
This application is a 371 of PCT/FI94/00439 filed Sep. 30, 1994.
BACKGROUND OF THE INVENTION
The invention relates to a method for testing an integrated circuit, the circuit comprising testing means for testing the circuit card and/or other circuits connected to the integrated circuit after it has been assembled onto the circuit card, inputs for controlling the testing means, and test structures for testing the internal operations of the integrated circuit. The invention also relates to an integrated circuit, comprising testing means for testing the circuit card and/or other circuits connected to the integrated circuit after it has been assembled onto the circuit card, inputs for controlling the testing means, and test structures for testing the internal operations of the integrated circuit.
The invention relates in particular to the testing of the internal operation of an ASIC circuit conducted by a circuit manufacturer in connection with the manufacturing. The aim of this test is to check the operation of the circuits by feeding test data into the inputs of the circuit, after which signals obtained from the outputs of the circuit are monitored. To conduct these tests, so-called scan path test structures have been formed in the circuit during its manufacturing, the test structures being intended solely for in-circuit testing. A separate pin, i.e. an input port, is reserved in the circuit for controlling the scan path test structures. Said pin has proved to be very problematic, since fitting it in the integrated circuit often calls for the use of a larger housing. Scan path testing is described, for example, in Digital Systems Testing and Testable Design (by M. Abramovic, M. A. Breuer & A. D. Friedman, Computer Science Press, New York, USA), and therefore it is not described in greater detail in this connection.
In addition to the testing of the internal operation of a single integrated circuit, the entire circuit card onto which the integrated circuit is assembled is also usually tested. For this purpose, test logic needed in particular for this type of testing is built into the integrated circuits. For example, in the ASIC circuits, it is possible to use boundary scan blocks according to the IEEE Standard (The Institute of Electrical and Electronics Engineers, Inc.) 1149.1, the blocks being applicable, among other things, in testing the connections between components assembled onto the circuit board. For the purpose of conducting these tests, the ASIC circuits comprise special pins, i.e. input ports, for controlling the tests.
With an increasing demand for smaller and smaller integrated circuits, it has proved to be necessary to limit the number of pins, i.e. inputs and outputs, in the circuits, since in practice they have a very significant effect on the size of the housing of the integrated circuit. The use of a larger housing may in turn lead into situations, where the size of that circuit card onto which the integrated circuit is to be assembled is too small, wherefore a larger circuit card has to be used.
SUMMARY OF THE INVENTION
The purpose of this invention is to provide a method by means of which the internal structures of an integrated circuit can be tested without, for enabling the testing, having to add extra pins to the circuit. These aims are achieved with a method according to the invention, which is characterized in that a test mode is defined for the testing means, in which test mode one of the inputs of the testing means is connected to the test structures for the internal operations of the integrated circuit, and that when the internal operations of the integrated circuit are tested, the testing means are set in the test mode, whereupon the internal test structures of the integrated circuit can be controlled from the input of the testing means.
The invention is based on the idea that when the test structures required for testing the internal operations of the circuit are connected with the testing means intended for the testing of the connections between the circuits on the circui
REFERENCES:
patent: 4479088 (1984-10-01), Stopper
patent: 4817093 (1989-03-01), Jacobs
patent: 4961053 (1990-10-01), Krug
patent: 5053700 (1991-10-01), Parrish
patent: 5109190 (1992-04-01), Sakashita et al.
patent: 5241266 (1993-08-01), Ahmad et al.
Abramovici, Miron et al., Digital Systems Testing and Testable Design, Nov. 1991, pp. 12-17.
IEEE Standard Test Access Port and Boundary-Scan Architecture, May 21, 1990 .
Karlsen Ernest F.
Nokia Telecommunications Oy
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