Method and device for synchronizing the receiver clock in a data

Details Method and device for synchronizing the receiver clock in a data Method and device for synchronizing the receiver clock in a data

1976-04-08

1977-08-02

Safourek, Benedict V.

Telegraphy

Systems

Line-clearing and circuit maintenance

328153, H04L 702

Patent

active

040397483

ABSTRACT:
A clock setting circuit is provided at a receiving modem for adjusting the phase of a timing signal defining the signal sampling instants. The received signal is filtered in two filters to derive a first signal having a phase .phi..sub.1 and a frequency f.sub.1 equal to f.sub.c - 1/2T, f.sub.c being the carrier frequency and 1/T being the transmission baud rate, and a second signal having a phase .phi..sub.2 and a frequency f.sub.2 equal to f.sub.c + 1/2T. The first and second derived signals are combined to derive an error signal indicative of the phase difference .phi..sub.2 - .phi..sub.1 which difference is used for adjusting the phase of a phase locked oscillator which provides the timing signal.

REFERENCES:
patent: 3372335 (1968-03-01), Takada
patent: 3378770 (1968-04-01), Daquet
patent: 3743775 (1973-07-01), Hutchinson

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