Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-06-06
2003-05-06
Nguyen, Vinh P. (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S765010
Reexamination Certificate
active
06559666
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to the testing of semiconductor chips and wafers and, more particularly, to a method and device for testing a chip or wafer without damaging contact points on the chip or wafer while providing a reliable electrical conductive path from each contact point on the chin or wafer to a corresponding point on a testing substrate.
BACKGROUND OF THE INVENTION
Most modern electronic systems include one or more integrated circuit (IC) chips bonded to a suitable substrate which, in turn, is connected to an electronic package such as a module, card, board, or gate. There are a variety of known techniques for connecting the chips to a substrate such as a circuit board. An overview of some of these techniques follows.
FIG. 1
shows one prior art technique for attaching an IC package
100
to a circuit board
105
. In this particular case, the IC
110
itself is inside a plastic, dual, in-line package
100
having bent metal leads
115
. (For convenience, an individual IC
110
is often referred to as a “die.”) Wire leads
120
are used to connect the IC
110
to the bent leads
115
of the package
100
. To mount the package
100
, the leads
115
are inserted into matching holes
125
in the circuit board
105
and fixed in place by solder.
FIG. 2
shows another prior art technique of attaching an IC to a circuit board generally known as the “solder-bump” approach. In this technique, the die
110
has metal pads on which small bumps of solder
130
are deposited. The die
110
is aligned over matching metal pads
135
on the circuit board
105
. When the assembly is heated to above the melting point of solder
130
, the solder melts to form an electrical contact between the IC
110
and the circuit board
105
. In this configuration, the die
110
is upside down from what is shown in FIG.
1
. Thus, the configuration is also known as a “flip-chip.”
Closely related to die connection technology is the increasing use of multi-chip module (MCM) design and packaging. In short, MCM techniques seek to combine a number of different dies on a common substrate. Benefits of MCM systems include increased operating clock speeds and reduced product footprint. Some in the semiconductor industry predict that as “real estate” (i.e., surface area) on IC devices continues to shrink, flip-chip bonding techniques will become dominant. Some of the benefits of the flip-chip bonding technique over wire bonding or tape automated bonding techniques—two other common die connection methods—are summarized in Table 1. Tape automated bonding is presently a preferred method of bonding dies to MCM-like substrates.
TABLE 1
Comparison of Typical Die Connection Characteristics
Tape Automated
Flip-Chip
Wire Bonding
Bonding
Resistance (Ohms)
0.002
0.030-0.035
0.020
[smaller is better]
Inductance (nH)
0.200
0.65
2.10
[smaller is better]
Capacitance (pF)
0.001
0.006
0.040
[smaller is better]
Example Bond Size,
400
472
520
one side (mils)
[smaller is better]
As shown in Table 1, the flip-chip technique requires less bonding area (for a given size die, e.g., 400 mils on a side) than do either wire or tape automated bonding methods. This advantage allows, in turn, for an increased packing density of dies on an MCM substrate. Flip-chip bonding also provides lower levels of resistance, capacitance, and inductance per contact than do the other methods. All of these features support increased operational speeds.
A significant problem in assembling MCM systems, or other multi-die circuits, is that dies purchased from silicon foundries usually cannot be assumed to be 100% “good” (i.e., functional). In a large multi-die circuit, the probability that a completed circuit will contain all good dies decreases exponentially as the number of dies increases. A significant problem for companies that assemble dies into circuits, e.g., system houses, is that of testing purchased dies to ensure that they are in fact good.
From the point of view of the system house, the problem is being able to obtain dies that are “known good” so that the system house does not have to incur the cost of testing each purchased die. On the other hand, silicon foundries make their money in running wafers and often do not want to perform costly functional testing. (A plurality of chips or dies are formed on a single wafer, during semiconductor manufacturing, which is then diced.) Many silicon foundries might be willing to perform, at most, a worst-case DC test at the wafer level.
If a system house avoids testing in manufacturing a one-hundred die MCM, for example, and any one or more of the dies are bad, the system house incurs the added costs of fault isolation and die removal and replacement—a possibly time-consuming and costly endeavor. Because of the costs of these operations, all of the forward-thinking semiconductor companies are now developing capabilities to perform bare die testing in preparation for flip-chip applications.
In semiconductor manufacturing, after a plurality of chips are formed on a wafer, each of the chips are commonly probed in sequence to initially check certain of their electrical characteristics. Following this initial probing, the wafer is diced, then packaged and subjected to a burn-in acceleration test to remove those products subject to initial failure. This acceleration test simulates long-time performance by operating a circuit at an elevated temperature (typically about 150° C.) while selected signal patterns and sequences are applied to the circuit. As MCM designs become more prevalent, new ways to conduct burn-in tests become more urgent, especially because replacement of faulty chips in an MCM is difficult to automate and a reworked MCM is typically not as reliable as an MCM which was not reworked. Disposal of an MCM having a single faulty chip is costly and, therefore, is not a desirable solution.
The processes of mounting individual dies to substrates or sequentially testing individual chips before they are diced are time consuming and costly alternatives. A considerable amount of time can be saved by testing an entire wafer at once. Accordingly, such all-encompassing tests are desirable.
These tests usually incorporate a test probe. One type of conventional test probe has a plurality of fixed needles mounted on respective cantilevered tungsten wires supported on an epoxy substrate. The wires are connected to an external tester and the needles are brought into contact with respective ones of the chip input/output (I/O) pads. Thus, the needles serve as contact electrodes. This needle and cantilevered wire arrangement, although used for many years in the semiconductor industry, is not suitable for high-density products. It has also been found that, when the chip under test is heated during burn-in testing, thermal expansion differences between the needles, the cantilevered wires, and the chip prompt the needles to shift from their original position. This thermal shifting is especially exaggerated when the chips are being tested in wafer (i.e., un-diced) form and can cause false readings or inputs. Thus, this probe technology is ill-adapted for reliable burn-in testing before dicing.
One attempt to meet the new requirements of testing MCM technology was disclosed by U.S. Pat. No. 5,625,298 issued to Hirano et al. (discussing T. Tada et al., “A Fine Pitch Probe Technology,” 1990 International Test Conference, pages 900-06). In this attempt, probe contact electrodes were formed on the surface of a glass board by a lithographic technique. Each contact was electrically connected to an external tester via a respective conductive via passing through a hole on the board. The metal contact electrodes are stiff, however, and do not allow for significant—although small—variations in the co-planarity of the wafer contacts. Consequently, the metal contact electrodes cannot compensate for small variations in the thickness of wafer metallizations or substrate pads, or perturbations in the surface of a wafer or substrate, not to mention solder bumps. Mor
Bernier William E.
Gaynes Michael A.
Howell Wayne J.
Pierson Mark V.
Trivedi Ajit K.
Nguyen Vinh P.
RatnerPrestia
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