Method and device for pulse density modulation

Details Method and device for pulse density modulation Method and device for pulse density modulation

2001-09-24

2003-05-13

Mis, David C. (Department: 2817)

Modulators

Pulse or interrupted continuous wave modulator

C332S112000, C341S144000, C375S239000

Reexamination Certificate

active

06563393

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method and device for pulse density modulation, that is for generating from an input value an output digital signal in which represents the input value by the density of digital pulses.
BACKGROUND OF THE INVENTION
Many applications require conversion of a series of multi-bit digital signal into a pulse density signal. For example, in many telecommunications applications, the receiver converts the received digitally encoded voice signal to analogue audio, reproducing the original voice sounds. In some feedback control circuits, the control signal is calculated and represented as a multi-bit digital signal, and this signal should be converted to an analogue signal to control the controlled devices. One way to convert the multi-bit signal to analogue signal is to convert the multi-bit signal to a pulse density signal first, and then filter the pulse density signal to analogue signal by an RC filter.
We now describe the function of a known pulse density modulator (PDM), A more detailed discussion is given in U.S. Pat. No. 5,337,338, the disclosure of which is incorporated herein by reference. The PDM receives a series of digital clock signals separated by a period p
w
, and a multi-bit digital signal representing an input value. From these two inputs, the PDM generates a 1-bit digital signal, i.e. a signal with just two possible voltage values, which we may refer to as 0.0V and V
OH
. Any time interval of length p
w
for which the voltage output of the PDM is a certain one of these values (generally, the higher one, V
OH
) is referred to as a pulse, so that the pulse density in the output signal is the proportion of the output signal which takes the voltage value V
OH
. The PDM is arranged such that the output signal has a pulse density proportional to the input value. Thus, the multi-bit input signal has been converted to a 1-bit signal.
In certain applications, the output signal is converted to an analogue signal corresponding to the (digital) input signal. If the clock frequency used to generate the pulse is high enough relative to the frequency of the incoming signal, the information lost can be within a tolerable range. Usually only 2 passive components (a resister and a capacitor) for an RC filter, are required to provide a low-ripple analogue signal.
A number of varieties of PDMs are known. One of these, described in U.S. Pat. No. 5,337,338, is illustrated in FIG.
1
. This PDM processes an N-bit digital input signal
4
. An N-bit counter
20
receives a high-rate clock signal
1
. The output of the N-bit counter
20
at every clock cycle is inverted (shown schematically by the region
22
) and fed (as input Q) to an N-bit comparer
24
, which also receives (as input P) the N-bit input signal
4
. If P is greater than or equal to Q, the output of the comparer
24
is voltage high; otherwise it is low.
The N-bit input value represented by the input signal
4
will be in the range 0~2
N
−1. If the input value is stable at x, then during the period of the counter
20
, that is 2
N
clock cycles (i.e. a time period of 2
N
p
w
), the output of the comparer
24
is high for x+1 of the 2
N
clock cycles, i.e. for a total time equal to the x+1 multiplied by p
w
. Note that the output of the counter
20
and the comparer
24
are each periodic with a length of 2
N
clock cycles. The purpose of the bit inversion
22
is to uniformly distribute the times at which the voltage output of the comparer
24
is high uniformly through the period of the counter.
If the arrangement of
FIG. 1
is varied so that the output of the comparer
24
is high only if “P>Q” (instead of “P>=Q”), there will be x pulses in the period of the counter. Thus, the output pulse number in one period of the counter can be set to 0 to 2
N
−1, or 1 to 2
N
, according to the setting of comparer
24
.
U.S. Pat. No. 5,995,546 proposes an alternative PDM illustrated in FIG.
2
. In this case the N-bit input signal
4
is passed to an adder
30
. The adder
30
also receives an N-bit input from an N-bit register
32
. At each clock cycle, the adder
30
adds the input signal
4
and the signal from the register
32
. The N-bit result of the addition is sent back to the register
32
. The register
32
also receives a clock signal, and the content of this register is updated at each clock cycle. If the addition operation results in an overflow then the value (voltage high) is sent to a 1-bit latch
34
, which is also controlled by the clock signal. If the addition operation resulted in no overflow, the value sent to latch
34
is voltage low.
If input value is stable at x, the output of the latch
34
is a periodic repetition with a length of 2
N
clocks cycles. In each 2
N
clock cycles, there are x pulses. Thus, this system can output a number of pulses in one period in the range 0 to 2
N
−1. If for some applications, an output range of 1 to 2
N
is needed, one method is to change the input from x to 2
N
−x (i.e. each bit is inverted from “1” to “0” or “0” to “1”) and invert the output bit in the same way.
Comparing with in U.S. Pat. No. 5,337,338, the PDM in U.S. Pat. No. 5,995,546 has the better performance because it has a more uniformly distribution of output pulses. For example, it is preferable for the PDM to have an output like “ . . . 10101010 . . . ”, rather than “ . . . 11001100 . . .”, even though their output pulse densities are the same, 50%, since in the former case the ripple after passing through the RC circuit will be lower.
SUMMARY OF THE INVENTION
As discussed above, in some applications, the PDM output signal is used to control an analogue device. In these conditions, the performance is improved if the output of the PDM has a pulse density according to a linear transformation of the input value. This is because most voltage-controlled analogue devices require that the input control voltage range, which is a fractional portion of power supply, is within a limited range.
The limitation of PDM output range may be caused by a limited dynamic range in the input controlling signal to the controlled device, or, caused by a requirement of whole system. One way to limit the range of the PDM output, is to limit the input range to the PDM; for example, to apply a hard clipper before PDM or a linear transformation before the PDM (with a multi-bit multiply and add operation). However both methods will cause degradation of resolution of the PDM (average output range/input range). This invention aims to make it possible to limit the range of the PDM output by applying a linear transformation within the PDM. One advantage of this is to avoid the resolution degradation caused by the limited input range. It also avoids the multi-bit multiply and adder operation required to perform a linear transformation before the PDM.
In its most general terms the present invention proposes a pulse density modulator unit which converts a series of multi-bit input signal representing an input value, into an output digital signal which represents an output value as a digital pulse density. The output value is a linear function of the input value.
The pulse density modulator unit includes a combination module which receives the input signal, and also a signal which encodes a multiplication factor as a pulse density. The combination module combines its inputs, and so produces a combined signal which, on average, depends on the input signal multiplied by the multiplication factor. Please note that this multiplication is very simple since one of the inputs is only 1 bit. A pulse density modulator uses the combined signal to generate the output digital signal.
Thus, the input value (which may take any of 2
N
values) may be transformed by means of the invention into any range of output values, such as a range of values less than 2
N
wide. Even in this case, the average value of the combined signal can take any one of 2
N
values within this range (i.e. values spaced apart by less than 1) according to the input value, and this freedom

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