Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Lateral bipolar transistor structure
Reexamination Certificate
2001-02-27
2003-09-23
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Lateral bipolar transistor structure
C257S552000, C257S561000, C257S573000
Reexamination Certificate
active
06624502
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor integrated circuits with junction isolation and, in particular, to a method and a device for reducing parasitic effects in semiconductor integrated circuits. Particularly but not exclusively, the present invention concerns a device for limiting the substrate potential in junction isolated integrated circuits.
BACKGROUND OF THE INVENTION
As is well known by one skilled in the art, in junction insulated integrated circuits the substrate is held at a reference potential by contacts which are typically placed on the bottom surface of the substrate. The bottom of the substrate is commonly referred to as the back of the integrated circuit. Each integrated circuit region doped opposite from the substrate is normally biased to a higher potential than the reference potential. Such an integrated circuit region is typically formed on the top surface of the substrate. The top surface of the substrate is commonly referred to as the front. The various regions of the integrated circuit are isolated electrically by reverse biased P-N junctions.
During operation, transient bias conditions may occur and cause the undesired flow of currents in the substrate of the integrated circuit. These currents are conventionally attributed to the activation of parasitic bipolar transistors, which may either be of the PNP type or the NPN type. Such transient bias conditions are mostly experienced upon a change of polarity on inductive loads such as inductors and motors, or on capacitive loads such as capacitors, batteries and rechargeable batteries.
In particular, transient bias conditions may cause electrons or holes to be injected into the substrate and generate parasitic currents therein. Electrons can be injected into the substrate, for example, when an N-type region is forward biased in the P-type substrate. In such a case, electrons may reach the substrate contact areas toward the referring potential and recombine with the substrate holes, or reach another N region which is reverse biased with respect to the substrate. Particularly in the latter case, as the electrons reach a reverse biased N-type region, a parasitic bipolar transistor known as a lateral NPN transistor becomes activated.
For example, holes can be picked up by the substrate when a P region inside an isolated region of the N-type is forward biased with respect to the N-type isolated region, itself reversed biased with respect to the substrate. The holes are injected from the P region into the N region. A portion of the holes may recombine with electrons present in the N-type region, and another portion can be picked up by the substrate. In the latter case, the collected holes within the substrate are responsible for a parasitic bipolar transistor, known as a vertical PNP transistor, being activated.
The substrate holes can migrate to the areas of contact with the reference potential, typically located on the substrate back. This current can locally raise the potential at the substrate front. The locally raised substrate potential may forward bias, with respect to the substrate, N-type regions which are normally reversed biased with respect to the substrate. The situation may activate structures of the PNPN type and trigger local currents with a current density capable of destroying the integrated circuit.
A first prior approach to lessening the effects of activating vertical PNP parasitic transistors comprises, as shown in
FIG. 1
, one or more connections
1
to the reference potential on the front of the substrate
2
, and additionally to the connection
3
to the reference potential which is located on the back of the integrated circuit. The connections
1
to the reference potential constrain the substrate potential, at least locally, to the value of the reference potential. This prevents the substrate potential from attaining suitable values for activating lateral NPN parasitic transistors, for example.
However, the connections
1
to the reference potential placed on the integrated circuit front can become, in the presence of a lateral NPN parasitic transistor, a preferential path for the base current of the NPN parasitic transistor, thus enhancing the transistor efficiency.
The underlying technical problem of the present invention is to provide a device and a related method for limiting the substrate potential with appropriate structural and functional features suitable to stop the substrate potential from exceeding the reference potential by a predetermined amount. This thereby avoids the inception of parasitic currents and overcomes the limitations and/or drawbacks of devices formed according to the prior art.
SUMMARY OF THE INVENTION
The concept behind the present invention is to provide a unidirectional element on the conduction path between the substrate and the reference potential, whereby the substrate potential is limited to a value only slightly above the reference potential, and every current flow likely to activate parasitic transistors, particularly of the lateral NPN type, is interrupted.
Based upon this concept, the technical problem is solved by a device comprising at least one unidirectional element connected between the substrate and the reference potential. The technical problem is also solved by a method of locally limiting the potential at the substrate surface in an integrated circuit. The method provides for a unidirectional element to be connected between the substrate surface and the reference potential.
REFERENCES:
patent: 5729040 (1998-03-01), Sano
patent: 5942783 (1999-08-01), Brambilla et al.
patent: 6194764 (2001-02-01), Gossner et al.
patent: 3507181 (1986-09-01), None
patent: 0678919 (1995-10-01), None
patent: 0847089 (1998-06-01), None
patent: 01261856 (1989-10-01), None
Patent Abstracts of Japan, vol. 008, No. 119 (E-248), Jun. 5, 1984 & JP 59 032150 A (Tokyo Shibaura Denki KK), Feb. 21, 1984.
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Jorgenson Lisa K.
Lee Eddie
STMicroelectronics S.r.l.
Warren Matthew E.
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