Coded data generation or conversion – Converter calibration or testing
Reexamination Certificate
2002-06-20
2003-11-04
Young, Brian (Department: 2819)
Coded data generation or conversion
Converter calibration or testing
C341S118000
Reexamination Certificate
active
06642870
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention concerns analog to digital converters and relates more particularly to the integration of a self-test module which makes it possible to measure the functional characteristics of the converter, such as shift, gain, non-linearities and others, using the histogram test principle.
DESCRIPTION OF THE PRIOR ART
With regard to the testing of analog to digital converters, manufacturers mainly use two methods, namely the histogram test and the Fast Fourier Transform (FFT) test.
The use of these methods requires very expensive high-performance external test equipment in the form of an industrial tester.
A conventional solution for reducing the cost of this external test consists of integrating test modules inside the circuit itself.
It is accepted that this type of solution is economically viable in so far as the surface area of the added modules represents only 10% to 15% of the original surface area of the circuit.
The integration of a histogram test device in its conventional form poses a problem since the surface area of the added test modules is excessive having regard to the extremely high volume of data to be stored on the one hand and the complex operations to be performed to allow use on the other hand.
SUMMARY OF THE INVENTION
The invention aims to remedy this drawback by redefining the histogram test technique so as to have only a small number of items of information to be stored on the integrated circuit and to evaluate the characteristics of the converter using simple operations.
It also aims to produce an integrated test module occupying a small surface area so as to make the histogram test solution economically advantageous.
According to one aspect of the present invention, there is provided a method of testing an analog to digital converter by histogram, consisting of decomposing in time, accumulation and use of the histogram, wherein the method of testing uses common resources for successively processing functional characteristics of the analog to digital converter and wherein the method of testing further consists of successively initializing and configuring said resources to adapt them to the determination of each of the functional characteristics of said converter.
According to another aspect of the present invention, there is provided a self-test device for an analog to digital converter for implementing a method of testing the analog to digital converter by histogram, consisting of decomposing in time, accumulation and use of the histogram, wherein the method of testing uses common resources for successively processing the functional characteristics of the analog to digital converter and wherein the method of testing further consists of successively initializing and configuring said resources to adapt them to the determination of each of the functional characteristics of said converter; the self-test device comprising:
means of applying test signals to the converter, and analysis means, wherein:
said analysis means include integrated and configurable common resources for successively determining the functional characteristics of the converter and means of configuring said common resources with a view to adapting them to the characteristics to be determined.
The device may have a reference code counter/comparator connected to the output of the analog to digital converter, a use and storage counter/downcounter whose output delivers signals relating to the functional characteristics of the converter and a controller for managing the test phases by means of the counter/comparator and the counter/downcounter.
REFERENCES:
patent: 5793642 (1998-08-01), Frisch et al.
patent: 5854598 (1998-12-01), De Vries et al.
patent: 0 336 715 (1989-10-01), None
XP-000409779, Custom Integrated Circuits Conference, MOK et al, “Strech: Self Testing Reliability Evaluation Chip”, 1993, pp. 30.4.1-30.4.4.
XP-0004007233, Microelectronics Jounral 27, “Embedded ADC Characterization Techniques Using a Bist Structure, An ADC Model and Histogram Data ”, 1996, pp. 539-549.
Azais Florence
Bernard Serge
Bertrand Yves
Renovell Michel
Centre National de la Recherche Scientifique (C.N.R.S.)
Lauture Joseph
Young Brian
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