Method and device for improving utilization of a bus

Details Method and device for improving utilization of a bus Method and device for improving utilization of a bus

2005-12-27

2005-12-27

Lamb, Twyler M. (Department: 2622)

Facsimile and static presentation processing

Static presentation processing

Memory

C358S001150, C358S001170, C710S100000, C710S119000, C710S305000

Reexamination Certificate

active

06980314

ABSTRACT:
An embodiment of a bus management device permits scheduling of transactions to allow concurrent execution of the transactions. Data bus usage is scheduled by setting shift register bits. Each position in the shift register corresponds to one clock cycle. When a current transaction is in a data phase, the value in the shift register is used to determine when to begin a control phase of the next transaction so that a desired number of idle clock cycles are present between data bus usage time periods for successive transactions.

REFERENCES:
patent: 5581782 (1996-12-01), Sarangdhar et al.
patent: 5812803 (1998-09-01), Pawlowski et al.
patent: 6032214 (2000-02-01), Farmwald et al.
patent: 0300228 (1991-10-01), None

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