Method and device for generating check bits protecting a data wo

Details Method and device for generating check bits protecting a data wo Method and device for generating check bits protecting a data wo

1982-03-16

1984-05-22

Atkinson, Charles E.

Excavating

G06F 1110

Patent

active

044505612

ABSTRACT:
Each of the check bits of an ECC codeword is generated in parallel in a byte serial sequence to permit structuring of the ECC device so that it has general application. For this purpose a byte wide check bit generator is provided for each of the check bits. These check bit generators contain generalized gating logic controlled by stored data that is capable of passing any combination of the bits making up the byte. As each byte enters such a check bit generator, the data controlling the gating logic is changed to generate a partial sum of the check bit using only those data bits from that data byte designated by the H matrix on the ECC. The partial check bits are then accumulated modulo 2 to generate the check bit to be stored with the data bits.

REFERENCES:
patent: 4160236 (1979-07-01), Oka et al.
patent: 4312068 (1982-01-01), Goss et al.
Ross, Parallel Cyclic Redundancy Check Using Programmable Logic Array, IBM Technical Disclosure Bulletin, vol. 19, No. 8, Jan. 1977, pp. 3068-3070.

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