Method and device for generating a clock signal using a...

Details Method and device for generating a clock signal using a... Method and device for generating a clock signal using a...

2007-10-16

2007-10-16

Mis, David (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

C331S011000, C331S017000, C331S025000

Reexamination Certificate

active

11194770

ABSTRACT:
A method and a device for generating a clock signal (Fout) are provided, wherein a digital phase difference signal (X) is formed depending on a phase difference between a reference clock signal (Fin) and a feedback signal (Ffb) derived from the clock signal (Fout) and wherein the digital phase difference signal (X) is digitally filtered, in order to form a digital filtered phase difference signal (U). A digitally controlled oscillator (5) is activated by a digital control signal dependent on the digital filtered phase difference signal (U) to generate the clock signal (Fout). With a device of this kind clock signals with frequencies in the gigahertz range can be generated with a minimum of analog circuit parts.

REFERENCES:
patent: 5036294 (1991-07-01), McCaslin
patent: 5488627 (1996-01-01), Hardin et al.
patent: 6970046 (2005-11-01), Da Dalt et al.
patent: 2005/0077969 (2005-04-01), Lalt et al.
patent: 2006/0050830 (2006-03-01), Da Dalt et al.
patent: 100 22 486 (2002-01-01), None
Ramezani et al., “Analysis of a Half-Rate Bang-Bang Phase-Locked-Loop”, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 49, No. 7, Jul. 2002, pp. 505-509, (5 pages).
Olsson, Thomas, “A Digitally Controlled PLL for SoC Applications”, IEEE Journal of Solid-State Circuits, vol. 39, No.5, May 2004, pp. 751-760, (10 pages).
Walker, R., “Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems,” Phase-Locking in High Performance Systems, IEEE Press, 2003, (12 pages).

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