Method and device for floating-point multiplication, and...

Details Method and device for floating-point multiplication, and... Method and device for floating-point multiplication, and...

2008-07-08

2008-07-08

Malzahn, David H (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

07398289

ABSTRACT:
In a method for multiplication of floating-point real numbers, encoded in a binary way in sign, exponent and mantissa, the multiplication of the mantissa envisages a step of calculation of partial products, which are constituted by a set of addenda corresponding to the mantissa. In order to reduce the size and power consumption of the circuits designed for calculation, there is adopted a method of binary encoding which envisages setting the first bit of the mantissa to a value 1, in order to obtain a mantissa having a value comprised between 0.5 and 1. Also proposed are methods for rounding of the product and circuits for the implementation of the multiplication method. Also illustrated are circuits for conversion from and to encoding of floating-point teal numbers according to the IEEE754 standard. Preferential application is in portable and/or wireless electronic devices, such as mobile telephones and PDAs, with low power-consumption requirements.

REFERENCES:
patent: 3871578 (1975-03-01), Van De Goor et al.
patent: 5128889 (1992-07-01), Nakano
Krandick, W., “Efficient Multiprecision Floating Point Multiplication with Optimal Directional Rounding,” IEEE Comput. Soc., Jun. 29, 1993, pp. 228-233.
Wires, K.E. et al., “Variable-Correction Truncated Floating Point Multipliers,” IEEE, vol. 2, Oct. 29, 2000, pp. 1344-1348.

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