Computer graphics processing and selective visual display system – Display driving control circuitry – Display power source
Reexamination Certificate
1999-05-05
2003-07-22
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Display driving control circuitry
Display power source
Reexamination Certificate
active
06597352
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to video synchronization input signals provided to a computer monitor or a video display unit.
BACKGROUND OF THE INVENTION
In a computer display or monitor, the main purpose of having horizontal synchronization pulses (H-sync) is to provide an accurate timing reference point to the horizontal scan circuit. In most of the cases, the sync pulses are fed from the CPU of a computer system into the monitor via a cable. This cable may contain a variety of signals that the monitor needs to show an image. The signal level of the H-sync is normally provided at +5V, but it may also be provided at about +3V depending on the transistor logic of the sync pulse generator. The triggering level that is used by the horizontal scan circuit in a monitor to start a horizontal scan is usually adopted from the TTL-standard. The polarity of the H-sync signals can be positive or negative. The horizontal sync signals, along with the vertical sync signals, are also used for power management to save electrical power in a monitor. The signaling between a CPU to a monitor is described in VESA (Video Electronics Standards Association) Display Power Management Standard (DPMS).
The stability of the video scan lines and the quality of the displayed image on a monitor depends on how precisely the line deflection is locked on the H-sync signals. In order to insure a good quality of the displayed image on the monitor, the horizontal scan circuit in the monitor should be immune to noise and interference which may exist in the cable connecting the CPU and the monitor. For that reason, it is important to choose the trigger level correctly.
Usually video synchronization signals are buffered by means of a TFL-compatible logic IC. For example, the 74HCT-series logic is often used for buffering H-sync signals. The H-sync signals can be fed directly into a deflection control IC (e.g. TDA9109) or into a micro-controller (e.g. ST7275) of the monitor which includes sync buffering. In these cases the triggering level is a fixed value, within a specified range of +0.8 to 2.2V. It is well known that a sync pulse has a leading edge and a trailing edge and either edge can be used to trigger a line scan. Because of the wiring capacitance in the connection cable, neither edge is very sharp as the pulse transients in the sync pulse are caused by the capacitance to slow down exponentially. As can be seen from
FIGS. 1A and 1B
, each of the edges of the sync pulse has a steep slope portion leading to a gradual slope portion. If the triggering level is located within the steep slope portion of the edge, the horizontal scan is reasonably immune to noise and interference. If the triggering level is located in the gradual slope portion, the horizontal scan is more susceptible to noise. In the latter case, noise and interference may cause a jitter in the horizontal scanning frequency and the overall instability of the displayed image. As shown in
FIG. 1A
, the polarity of the sync pulses is positive and the triggering level is located within the steep slope portion of the leading edge. However, on the trailing edge, the triggering level is located at the gradual slope portion, and, in this case, the trailing edge may not be suitable to be used as the triggering means for horizontal scans. The opposite is true for the sync pulses of negative polarity. As shown in
FIG. 1B
, the triggering level is located within the steep slope portion of the trailing edge, but in the gradual slope portion of the leading edge. Depending on which edge is used for triggering, the jitter in the horizontal scanning frequency may yield unacceptable visual effects, especially in high end monitors.
The typical length of the cable which is used to connect a CPU to a monitor for providing video signals is about 1.5 meter. The capacitance of the cable is usually large enough to distort the sync pulses, causing unacceptable visual effects, especially in high-end monitors having a high synchronization frequency over 60 kHz. Moreover, cable impedance and the input impedance of the sync inputs of the display are not standardized. Thus, the output impedance of the display driver in the CPU, the impedance of the cable, and the input impedance of the display may not match to each other. This impedance mismatch also distorts sync pulses. The problem of sync pulse distortions occurs not only in a computer system having a cable to provide video information from the CPU to the video display, but also occurs in video equipment having a cable for connection and for carrying sync lines.
It is desirable to provide a method and a device to improve the synchronization in the horizontal scanning in a monitor or video equipment, regardless of the polarity of the synchronization signals.
SUMMARY OF THE INVENTION
It is an objective of the present invention to improve the consistency in line scanning in a video display device and the stability of the horizontal scanning frequency.
This objective can be achieved by providing a filtered sync signals detector between the H-sync signal input and the horizontal scan circuit of a monitor or video equipment. The method and device for filtered sync signals detection, according to the present invention, is to sort out the steep slope portion of one or both of the edges of an incoming H-sync pulse and set a triggering point in the steep portion of the edges.
The method and device for filtered sync detection, according to one version of the present invention, use a timing filter, such as an RC timing circuit, to select the steep slope portion of one or both of the edges in an incoming sync pulse, a voltage divider to set a triggering point within the steep slope portion of the selected edge, regardless of the slope being negative or positive, and a triggerable device or voltage comparator to generate a new sync pulse substantially in the form of a rectangular wave having a first edge and a second edge, wherein at least the first edge starts substantially at a triggering point.
The method and device for filtered sync detection, according to another version of the present invention, use a timing circuit to filter out the sync pulses in the incoming sync signals. The filtered signals are provided as a reference voltage to one input terminal of a voltage comparator, while the incoming sync signals are provided to the other input terminal of the voltage comparator. These signals are fed to the voltage comparator in order to adjust, or tune, the triggering point within the steep slope portion of the leading edge of the incoming signals.
In yet another version of the present invention, a voltage comparator is used as a triggerable device for generating new sync pulses from the incoming signals. A micro-controller is used to detect the polarity of the incoming sync pulses and accordingly provide a reference voltage to the voltage comparator in order to tune the triggering point within the steep slope portion of the triggering edge of an incoming sync pulse. The micro-controller receives signals from the output of the voltage comparator or from a deflection circuit for polarity detection. Based on the DC level of the incoming signals, the micro-processor provides a reference voltage level between the DC level and the sync pulse amplitude such that the difference between the reference voltage and the DC level is an appropriately small value.
The filtered sync signals detection method and device will become apparent upon reading the drawings and the accompanying descriptions.
REFERENCES:
patent: 4064541 (1977-12-01), Schneider et al.
patent: 4084187 (1978-04-01), Schlotzhauer et al.
patent: 4535294 (1985-08-01), Ericksen et al.
patent: 4580166 (1986-04-01), Okano
patent: 4677388 (1987-06-01), Morrison
patent: 5218533 (1993-06-01), Schanen
patent: 5519444 (1996-05-01), Ko et al.
patent: 5754250 (1998-05-01), Cooper
patent: 5798730 (1998-08-01), Sanchez
patent: 6018273 (2000-01-01), Tsyrganovich
patent: 1 051 029 (2000-08-01), None
Haapakoski Hannu
Salonen Vesa
Vigelius Kari
Hjerpe Richard
Laneau Ronald
Nokia Corporation
Ware Fressola Van der Sluys & Adolphson LLP
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