Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-04-13
2001-10-30
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185090, C365S185080, C365S189070, C365S189080, C365S195000, C365S204000, C365S230080, C365S233500
Reexamination Certificate
active
06310801
ABSTRACT:
TECHNICAL FIELD
The present invention regards a method and a device for fast addressing of redundant columns in a nonvolatile memory.
BACKGROUND OF THE INVENTION
As is known, certain types of volatile memory (EPROM, EEPROM, Flash, etc.) enable replacement of faulty rows or columns of the memory array with others, referred to as “redundant” ones, in order to restore complete functionality of the memory array. In this case, the information on the presence of faulty rows or columns and on their position is stored in non-erasable memory cells known as CAM cells, which are read in the so-called phase of memory “power-up”, i.e., in the phase during which the supply voltage is supplied.
FIG. 1
illustrates a device for addressing redundant columns, which is widely used in nonvolatile memories.
The addressing device, designated as a whole by
1
, comprises a plurality of addressing circuits
2
, one for each redundant column to be addressed, only one of which being illustrated in FIG.
1
and being described in what follows.
The addressing circuit
2
comprises a detecting stage
3
receiving at inputs the addresses supplied to the memory and having the purpose of verifying whether a transition has occurred in said addresses, and supplying at outputs a masking control signal ATD and a discharging control signal PH.
In particular, the masking control signal ATD has a low-to-high logic level switching edge when a transition is detected in the addresses and a subsequent high-to-low logic level switching edge delayed with respect to the former switching edge by a preset length of time sufficient to enable the addresses to propagate within the addressing circuit
1
, as described more fully in what follows.
The discharging control signal PH is instead obtained by inverting the masking control signal ATD and delaying the second switching edge by a preset amount &Dgr; with respect to the second edge of the masking control signal ATD, the meaning of which will be clarified below.
The addressing circuit
2
further comprises a comparator stage
4
having the purpose of verifying whether the redundant column has been addressed. In particular, the comparator stage
4
receives at inputs the address ADI of the column of the array addressed and the address ADF of a respective redundant column of which it controls the addressing, compares one by one the n bits of the address ADI of the column addressed with the respective n bits of the address ADF of the redundant column, and supplies at output n status signals COMP[
1
. . . n] of a logic type each indicating the outcome of the comparison made on a respective pair of bits: if the redundant column has been addressed, all the status signals COMP[
1
. . . n] assume a low logic level whereas if the redundant has not been addressed, at least one of the status signals COMP[
1
. . . n] assumes a high logic level.
The addressing circuit
2
further comprises a masking stage
5
formed of n NMOS masking transistors
6
(only one of which illustrated in the figure) each presenting a drain terminal connected to a respective output of the comparator stage
4
and receiving a respective status signal COMP[
1
. . . n], a source terminal connected to ground and a gate terminal receiving the masking control signal ATD.
The addressing circuit
2
further comprises a discharging stage
8
formed of n NMOS discharging transistors
10
having drain terminals connected to one and the same common node
12
, source terminals connected to ground and gate terminals connected to respective outputs of the comparator stage
4
and receiving respective status signals COMP[
1
. . . n].
The addressing circuit
2
further comprises a precharging stage
14
comprising an NMOS pull-down transistor
16
and a PMOS pull-up transistor
18
. In particular, the pull-down transistors
16
and pull-up transistor
18
have drain terminals connected together and to the common node
12
, source terminals connected to a supply line
20
and, respectively, to ground, and gate terminals connected together and receiving the discharging control signal PH.
The addressing circuit
2
further comprises a storage stage
22
storing the logic level of the common node
12
, this stage being basically made up of a latch having an input terminal connected to the common node
12
, an output terminal on which it supplies the logic level of the common node
12
, and a control terminal receiving the discharging control signal PH.
The addressing circuit
2
further comprises a final stage
24
comprising a NOR logic gate
26
having a first input connected to the output of the storage stage
22
; a second input connected to the output of a NOT logic gate
28
on the input of which is supplied the discharging control signal PH; and an output on which an addressing signal YMi is supplied for the respective redundant column.
The addressing signal YMi is then supplied, as illustrated in
FIG. 2
, to a gate terminal of a respective NMOS selection transistor
30
arranged between the bit line
32
of the respective redundant column
34
, to which are connected the drain terminals of the memory cells of that column (the drain capacitances of which are represented schematically in the figure by an equivalent capacitor
36
), and a sense amplifier
38
responsible for precharging the bit lines
32
of the redundant columns
34
.
The addressing phase of a redundant column
34
will now be described with reference to
FIG. 3
, which illustrates the plots versus time of the status signal COMP [
1
. . . n], the masking control signal ATD, the discharging control signal PH, and the addressing signal YMi, as well as of the voltages of the common node
12
, indicated by VW, of the bit line
32
of the redundant column addressed, and of a bit line of a non-redundant column, indicated respectively by VCR and VCS, following upon a transition of the addresses supplied as input to the memory array.
As illustrated in
FIG. 3
, upon transition in the addresses supplied as input to the memory array, the masking control signal ATD switches from the low logic level to the high logic level, whilst the discharging control signal PH switches from the high logic level to the low logic level.
The masking control signal ATD, set at the high logic level, turns on the masking transistors
6
(so as to bring them into the triode region), thus imposing on the outputs of the comparator stage
4
a low logic level and hence, in practice, masking the outcome of the comparison.
Simultaneously, the discharging control signal PH at the low logic level turns on the pull-up transistor
18
and turns off the pull-down transistor
16
of the precharging stage
14
, thus bringing about charging of the common node
12
, the voltage VW of which, as a result, switches rapidly from a low logic level to a high logic level and, through the NOT logic gate
28
and the NOR logic gate
26
, maintains the addressing signal YMi at the low logic level regardless of the logic level supplied at output from the storage stage
22
.
In addition, with a slight delay with respect to the transition in the addresses, the bit lines of the non-redundant columns addressed start to charge and their voltage VCS starts to increase towards the final value to which they must be precharged.
The masking control signal ATD remains at the high logic level for a time long enough for the addresses to be propagated up to the comparator stage
4
, and then switches to the low logic level.
When the masking control signal ATD switches from the high logic level to the low logic level, the masking transistors
6
are turned off, the outputs of the comparator stage
4
are no longer bound to the low logic level, and the status signals COMP[
1
. . . n] are free to evolve towards the logic level corresponding to the outcome of the comparison.
At this point, if addressing of a redundant column
34
does not correspond to the transition of the addresses, then at least one of the status signals COMP [
1
. . . n] s
Condemi Carmelo
La Placa Michele
Martines Ignazio
Galanthay Theodore E.
Iannucci Robert
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
Tran Andrew Q.
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