Method and device for erasing non-volatile semiconductor memory

Details Method and device for erasing non-volatile semiconductor memory Method and device for erasing non-volatile semiconductor memory

1997-12-10

1999-08-03

Nelms, David

Illumination

Self powered lamp

Having plural lamp bulbs or lamp sockets

36518518, 36518519, G11C 1604

Patent

active

059315636

ABSTRACT:
An entire erasing period for a non-volatile semiconductor memory is divided into a first erasing mode and a second erasing mode. In the first erasing mode, a positive voltage is applied to sources of memory cells MC00 through MCmn with gates of the memory cells at a ground potential to carry out the erasing operation until an erasing voltage VTM2 that is higher than a final erasing voltage VTM1 is obtained. In the second erasing mode, negative and positive voltages are applied to the gates and the sources, respectively, of the memory cells to carry out the erasing operation until the final erasing voltage VTM1 is obtained.

REFERENCES:
patent: 4875188 (1989-10-01), Jungroth
patent: 5077691 (1991-12-01), Haddad et al.
patent: 5295107 (1994-03-01), Okazawa et al.
patent: 5309402 (1994-05-01), Okazawa
patent: 5485423 (1996-01-01), Tang et al.
patent: 5581502 (1996-12-01), Richart et al.

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