Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2001-11-28
2004-04-13
Wu, Xiao (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S063000, C345S691000
Reexamination Certificate
active
06720940
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and a device for driving an AC type plasma display panel.
A plasma display panel (PDP) has been widely used as a monitor of a television or a computer since a color screen was commercialized. As a using environment is diversified along with the widespread use, a driving method is desired that can realize a stable display without being affected by temperature variation or voltage regulation of a power source.
2. Description of the Prior Art
As a color display device, a surface discharge format AC type PDP is commercialized. The surface discharge format means a structure in which display electrodes (first electrodes and second electrodes) to be anodes and cathodes in display discharge for ensuring luminance are arranged on a front or a back substrate in parallel, and address electrodes (third electrodes) are arranged so as to cross the display electrode pairs. There are two arrangement forms of the display electrodes. In the first form, a pair of display electrodes is arranged for each row of a matrix display. In the second form, the first and the second display electrodes are arranged alternately at a constant pitch. In the second form, the display electrode except both ends of the arrangement works for displays of two rows. Regardless of an arrangement form, the display electrode pairs are covered with a dielectric layer.
In a display of a surface discharge format PDP, one of the display electrode pair (the second electrode) corresponding to a row is used as a scan electrode for selecting a row, so that address discharge is generated between a scan electrode and an address electrode, which causes address discharge between display electrodes. Thus, an addressing is performed controlling wall charge quantity in the dielectric layer in accordance with display contents. After the addressing, sustaining voltage Vs having alternating polarities is applied to the display electrode pair. The sustaining voltage Vs satisfies the following inequality (1).
Vf
XY
−Vw
XY
<Vs<Vf
XY
(1)
Here, Vf
XY
denotes discharge start voltage between display electrodes, and Vw
XY
denotes wall voltage between display electrodes.
By applying the sustaining voltage Vs, cell voltage (the sum of drive voltage that is applied to the electrode and the wall voltage) exceeds the discharge start voltage Vf
XY
only in cells having predetermined quantity of wall charge so that surface discharge is generated on the surface of the substrate. When the application period is shortened, light emission looks as being continuous.
A discharge cell of a PDP is basically a binary light emission element. Accordingly, a halftone is reproduced by setting integral light emission quantity of an individual discharge cell in a frame period in accordance with a gradation value of input image data. A color display is a type of the gradation display, and the display color is determined by combining luminance values of three primary colors. For the gradation display, a method is used in which one frame is made of plural subframes (subfields in the case of an interlace display) having luminance weights, and the integral light emission quantity is set by combining on and off of the light emission for each subframe.
FIG. 12
is a diagram of voltage waveforms showing a general driving sequence. In
FIG. 12
, reference letters X, Y and A denote the first display electrode, the second display electrode and the address electrode, respectively. Each of the numeric letters 1−n added to X and Y indicates the arrangement order of the row corresponding to the display electrodes X and Y. Each of the numeric letters 1−m added to A indicates the arrangement order of the column corresponding to the address electrode A.
A subframe period Tsf assigned to a subframe includes a reset period TR for equalizing charge distribution in the screen, an address period TA for forming the charge distribution in accordance with display contents by applying a scan pulse Py and an address pulse Pa and a sustain period (also referred to as a display period) TS for ensuring a luminance value corresponding to a gradation value by applying a display pulse Ps. The lengths of the reset period TR and the address period TA are constant regardless of a luminance weight, while the length of the sustain period TS is longer as the luminance weight is larger. The illustrated set of waveforms is an example. It is possible to modify the amplitude, the polarity and the timing variously.
In the reset period TR, a writing pulse Prx is applied to all the display electrodes X so that whole surface discharge is generated and the wall charge is erased by self-erasing discharge accompanied with the end of the pulse application. The address electrode A is supplied with a pulse Pra for preventing undesired discharge. There is a method for equalizing the charge distribution, in which a ramp waveform pulse is applied so as to control the charge quantity. In the address period TA, all the display electrodes Y are biased to non-selection potential Vya
2
at the start point in time, and then the display electrodes Y corresponding to the selected row i (1≦i≦n) are biased to selection potential Vya
1
temporarily (application of the scan pulse). In synchronization with the row selection, the address electrodes A are biased to the selection potential Vaa only in the column including the selected cells generating the address discharge of the selected rows (application of the address pulse). The address electrodes A of the column including the non-selected cells are biased to the ground potential (usually zero volts). The display electrodes X are biased to a constant potential Vxa from the start to the end of the addressing regardless of being the selected row or the non-selected row. In the sustain period TS, the display pulse Ps having the amplitude Vs is applied to the display electrode Y and the display electrode X alternately. The number of the pulse application is substantially proportional to the luminance weight.
In a PDP, internal electrification characteristics depend on operating temperature, so that a difference of the charged state can be generated between cells depending on a display pattern. As a result, the conventional driving method has a problem that an addressing error is apt to occur because of excessive or insufficient charge at interelectrode AY between the address electrode A and the display electrode Y. This problem will be explained as follows.
FIG. 13
is a diagram of waveforms showing cell voltage variation in the address period of the conventional method. In
FIG. 13
, thick solid lines indicate appropriate variation of the cell voltage (the sum of the applied voltage and the wall voltage), while chain lines indicate inappropriate variation of the cell voltage.
Here, the k-th cell in the selection order j-th row is noted. A display pattern is supposed, in which an address electrode A corresponding to the k-th column is biased to the address potential Vaa, i.e., the display data D
1,k
-D
i,k
of the k-th column and of the first through i-th rows are the selected data in the period before the noted row becomes the selected row and while the first through i-th (i<j) rows are the selected rows. The wall voltage at the interelectrode XY at the start point of the address period TA is denoted by Vwxy
1
, and wall voltage at the interelectrode AY at the start point of the address period TA is denoted by Vway
1
.
If the operating temperature is relatively low, the wall voltage does not alter before the noted row becomes the selected row remaining substantially at the initial value. Therefore, when the noted row becomes the selected row, and the display electrode Y
j
is biased to the selection potential Vya
1
, and when the address electrode A
k
is biased to the address potential Vaa, the cell voltage (Vway
1
+Vaa−Vya
1
) at the interelectrode AY exceeds a discharge threshold level Vf
AY
, so that address discharge is generated. Th
Awamoto Kenji
Takayama Kunio
Fujitsu Limited
Staas & Halsey , LLP
Wu Xiao
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