Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2001-09-10
2004-12-21
Nguyen, Jimmy H. (Department: 2673)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S066000, C345S067000
Reexamination Certificate
active
06833823
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and device for driving an AC type PDP.
2. Description of the Prior Art
A PDP (Plasma Display Panel) is widely used for a television or a computer monitor after a color screen was commercialized. As being widespread, the use environment has become diversified, and a driving method is desired that can realize a stable display without affected by temperature variation or voltage fluctuation of a power source.
As a color display device, an AC type PDP utilizing a surface discharge format has been commercialized. The surface discharge format has a structure in which display electrodes (first electrodes and second electrodes) to be anodes and cathodes in display discharge for securing luminance are arranged in parallel on a front or back substrate, while address electrodes (third electrodes) are arranged so as to cross the display electrode pairs. The arrangement of the display electrodes includes a form in which a pair of display electrodes is arranged for each row of a matrix display and another form in which the first and the second display electrodes are arranged alternately at a constant distance. In the latter case, each display electrode except ones at both ends of the arrangement works for two rows of display. Regardless of the arrangement form, the display electrode pairs are covered with a dielectric layer.
In the surface discharge format PDP display, one of the display electrodes (the second electrode) corresponding to each row is used as a scan electrode for row selection, so that address discharge is generated between the scan electrode and the address electrode, and the discharge causes another address discharge between the display electrodes. Thus, addressing is performed in which charge quantity in the dielectric (wall charge quantity) is controlled in accordance with display contents. After the addressing, a sustaining voltage Vs having alternating polarities is applied to the display electrode pair. The sustaining voltage Vs satisfies the following inequality (1).
Vf
XY
−Vw
XY
<Vs<Vf
XY
(1)
Vf
XY
: discharge start voltage between display electrodes.
Vw
XY
: wall voltage between display electrodes.
When the sustaining voltage Vs is applied, cell voltage (the sum of the drive voltage applied to the electrode and the wall voltage) exceeds the discharge start voltage Vf
XY
only in cells having a predetermined quantity of wall charge so as to generate surface discharge on the substrate surface. As the application period is shortened, the light emission can be seen continuously.
A discharge cell of the PDP is basically a binary light emission element. Therefore, a halftone is reproduced by setting integral light emission quantity of each discharge cell in a frame period in accordance with a gradation value of input image data. A color display is one type of the gradation display, and a display color is determined by combining luminance values of three primary colors. The gradation display is performed by a method in which one frame includes plural subframes (subfields in an interlace display) having a weight of luminance, and the integral light emission quantity is determined by combining on and off of light emission of subframes. For example, 256-gradation display can be achieved by dividing a frame into eight subframes having luminance weights of 1, 2, 4, 8, 16, 32, 64 and 128. In general, weighting of luminance is set by the number of light emission times.
FIG. 18
shows voltage waveforms of a general driving sequence. In
FIG. 18
, reference letters X, Y and A indicate a first display electrode, a second display electrode and an address electrode, respectively. Indices
1
-n of the reference letters X and Y indicate arrangement order of the row corresponding to the display electrodes X and Y. Indices
1
-m of the reference letter A indicate arrangement order of the column corresponding to the address electrode A.
The subframe periods Tsf assigned to subframes are classified roughly into a reset period TR for equalizing charge distribution on the screen, an address period TA for forming charge distribution corresponding to display contents by applying a scan pulse Py and an address pulse Pa and a sustaining period TS for securing luminance corresponding to the gradation value by applying a sustaining pulse Ps. The reset period TR and the address period TA have constant lengths regardless of the luminance weight, while the sustaining period TS has a variable length, which is longer as the luminance weight is larger. The illustrated waveform is an example. The amplitude, the polarity and the timing can be modified variously. The equalization of the charge distribution in the reset period TR can be achieved preferably by a method of controlling the charge quantity by applying a ramp waveform pulse.
FIG. 19
shows conventional driving voltage waveforms in the address period.
In the address period TA, an individual potential control is performed for each display electrode Y that is used as a scan electrode for row selection of an n×m screen. After biasing all the display electrodes Y to a non-selection potential Vya
2
at the start point of the address period TA, the display electrode Y corresponding to the selected row i (1≦i≦n) is temporarily biased to a selection potential Vya
1
(application of the scan pulse). The illustrated row selection order is the same as the arrangement order of the row. In synchronization with the row selection, the address electrodes A in the column of the selected cell that generates the address discharge in the selected row is biased to the selection potential Vaa (application of the address pulse). The address electrodes A in the column of the non-selected cell are set to the ground potential (usually zero volt). The display electrodes X are biased to a constant potential Vxa from the start to the end of the addressing regardless of the selected row or the non-selected row.
In a PDP, inner charge characteristics depend on operating temperature, so that different display patterns generate different charged states between cells. Therefore, it was a problem in the conventional driving method that an addressing error can occur easily due to excessive or insufficient charge at interelectrode AY of the address electrode A and the display electrode Y. This problem will be explained below.
FIG. 20
shows conventional waveforms of the cell voltage change in the address period. The thick solid line in
FIG. 20
indicates an appropriate change of the cell voltage (the sum of the applied voltage and the wall voltage), while the chain line indicates an inappropriate change of the cell voltage.
Here, cells in the k-th column and in the j-th row of the selection order are noted. It is supposed that the address electrode A corresponding to the k-th column is biased to an address potential Vaa before the noted row becomes the selected row and in the period while the selected row is the (
1
-i)th (i<j) row. In other words, a display pattern is supposed in which display data D
1,k
-D
i,k
of the first row through the i-th row in the k-th column are the selected data. The wall voltage at the interelectrode XY at the start point in the address period TA is denoted by Vwxy
1
, and the wall voltage at the interelectrode AY is denoted by Vway
1
.
If the operating temperature is appropriate, the wall voltage remains approximate initial value at the stage before the noted row becomes a selected row. Therefore, when the noted row becomes the selected row so that the display electrode Y
j
is biased to the selection potential Vya
1
and the address electrode A
k
is biased to the address potential Vaa, the cell voltage at the interelectrode AY (Vway
1
+Vaa−Vya
1
) exceeds the discharge threshold level Vf
AY
so as to generate the address discharge. The address discharge causes the wall voltage change both at the interelectrode AY and the interelectrode XY, so that the charged state suitable for the operation of the follow
Fujitsu Limited
Nguyen Jimmy H.
Staas & Halsey , LLP
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