Method and device for detecting a cyclic code

Details Method and device for detecting a cyclic code Method and device for detecting a cyclic code

1995-08-28

1998-06-09

Trammell, James P.

Excavating

371 377, H03M 730

Patent

active

057648760

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1) Field of the Invention
This invention relates to a method and device for detecting a cyclic code, and more specifically to means suitable for establishing synchronization in the ATM communication system.
2) Background Art
ATM (Asynchronous Transmission Mode), which is attracting attention as the switching system for broad-band ISDN (Integrated Services Digital Network), is a system which transmits data containing audio and visual information at a high speed by dividing it into predetermined length of blocks called cells and adding a header indicating the destination to each cell.
In the ATM system, a cell consists of 5 bytes for the header and 48 bytes for the information field, 53 bytes in total. The 5-byte or 40-bit header of a cell is a shortened cyclic code that consists of a 32-bit information point and an 8-bit checkpoint called HEC (Header Error Control).
The shortened cyclic code is generated in the following manner. First, 8 bits of 0s are concatenated to the 32 bits of the information bits to form a 40-bit code. Next, this 40-bit code is divided by generating polynomial X.sup.8 +X.sup.2 +X+1 to calculate the remainder. Since generating polynomial X.sup.8 +X.sup.2 +X+1 is 9 bits, the remainder is always equal to or less than 8 bits. This remainder is the check bits (CRC: Cyclic Redundancy Code). The remainder is then subtracted from the above 40-bit code (the result of bit-from-bit subtraction is equal to that of bit-to-bit addition). As the result, the previously added 8 bits of 0s are replaced by the remainder. In ATM, X.sup.6 +X.sup.4 +X.sup.2 +1 (bit pattern 01010101) is further added to the 40-bit codeword.
In ATM, boundaries between cells must be detected to correctly receive cells continuously on a transmission line at the receiving side. This process is called cell synchronization and performed by utilizing the header of cells. By dividing the 40 bits of the header of each cell by generating polynomial at the receiving side, X.sup.6 +X.sup.4 +X.sup.2 +1 that was added to the header at the transmitting side is obtained as the remainder. Detection of headers is performed by utilizing this principle.
When the receiver is not synchronized (in the hunting mode), it performs division on a 40-bit portion taken out of the received data one after another. If the remainder is X.sup.6 +X.sup.4 +X.sup.2 +1, the 40 bit portion is considered to be the header of a cell, and the receiver enters the pre-synchronization state (quasi-synchronized state).
If the remainder is not X.sup.6 +X.sup.4 +X.sup.2 +1, the same test is performed on the next 40 bits shifted by one bit. This test is repeated until the receiver enters the aforementioned pre-synchronization state.
In the pre-synchronization state, the receiver tests the 40 bits at the position 53 bytes (one cell) after the position considered at first to be the header of a cell for being a shortened cyclic code with X.sup.6 +X.sup.4 +X.sup.2 +1 added.
This test is performed on each possible cell. If the expected code is detected a predetermined number of times successively, then it is determined that the complete synchronization is established.
To implement the cell synchronization process described above, a divider 1 made up of an 8-bit feedback shift register as shown in FIG. 2 is used.
This divider 1 has exclusive OR circuits 5 put before the 1st stage, between the 1st and 2nd stages, and between the 2nd and 3rd stages of the shift register so that the result of the exclusive OR operation on the input to the 1st stage of the shift register and the fed back output of the last stage (8th stage) is input to the 1st stage, the result of the exclusive OR operation on the output of the 1st stage and the fed back output of the last stage is input to the 2nd stage, and the result of the exclusive OR operation on the output of the 2nd stage and the fed back output of the last stage is input to the 3rd stage.
These exclusive OR circuits 5 subtract the value of the output of the last stage from the value of the bit input to the shift

REFERENCES:
patent: 4566105 (1986-01-01), Oisel et al.
patent: 4677623 (1987-06-01), Iwasaki et al.
patent: 5046069 (1991-09-01), Calvignac et al.
patent: 5303245 (1994-04-01), Shikakura et al.

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