Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1999-11-30
2001-03-27
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S263000
Reexamination Certificate
active
06208184
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to read/write channels of mass data storage devices, for example of a hard disk drive, and more particularly, to a method and circuit of pre-compensation, during a write phase, of the effects of nonlinear intersymbol interference during a subsequent read phase of the recorded data.
BACKGROUND OF THE INVENTION
Due to the ever-growing density with which data must be stored on hard disks or similar magnetic media, it is useful, during the write phase of the data, to delay a transition, i.e. the switching of a bit from a low state to a high state or vice-versa, when in the immediately preceding clock phase there has been a transition in the opposite direction. This approach serves to compensate the shift of the physical position of the second transition towards the preceding transition already recorded on the hard disk. This anticipation (during a reading phase) of the second transition is mainly due to the so-called nonlinear intersymbol interference caused by the presence of a demagnetizing field produced by an immediately preceding transition, as well as by the partial data deletion in the transition zone due to the high density of data stored on the hard disk.
To implement this pre-compensation, i.e. to delay the transitions that immediately follow another transition, special circuitry is used comprising a delay circuit and a multiplexer to switch from the system clock to a slightly delayed clock to delay the output data stream. This switching is effected by a signal generated by a control circuit that identifies two transitions intervening in the input data stream as consecutive transitions.
Due to the generally high system clock frequencies, this type of approach has several drawbacks. A first drawback is that to operate at the system clock frequency, the delay circuit and the control circuit must be realized in ECL technology (Emitter Coupled Logic), with a consequent increase in the complexity and costs of the fabrication process compared to a typically preferred fully CMOS technology (Complementary Metal Oxide Semiconductor). A further drawback is that the multiplexer, operating at a high frequency, generates glitches that reduce the reliability of the device itself. Moreover, the delay circuit may delay the system clock for up to a half period, because greater delays would imply a write error at the instant of the switching from the delayed clock back to the system clock.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a pre-compensation method for overcoming such drawbacks and limitations of the conventional approach and provide an implementing circuit that may be realized in CMOS technology. These and other objects are achieved by the method and circuit of the present invention.
The method of the invention is for delaying a transition in a digital data stream directed towards a write head of a mass storage device by a certain time interval when the transition occurs at the clock pulse following the one during which a transition has already occurred, for pre-compensating for the effects of nonlinear intersymbol interference during a reading of the recorded data. The method includes feeding a first circuit with a digital data stream to be recorded and with a clock signal and outputting a pair of digital streams. The first stream assumes a first logic value every time a transition in the input stream occurs at a clock pulse not following a clock pulse during which a transition has taken place. The second stream assumes the first logic value every time a transition in the input stream occurs at a clock pulse that follows a clock pulse during which a transition has taken place.
The method also includes feeding the two digital streams and the clock signal to the inputs of a second circuit and outputting from the second circuit, the digital stream of data directed towards the write head. The transitions immediately successive to a preceding transition are delayed by the pre-established time interval, by sampling the two streams by a flip-flop pair, each of which is timed by a clock signal delayed by a respectively different time interval. The temporal difference between the different delay intervals is equal to a pre-established time interval, and the two signals output from the flip-flop pair are re-combined through an XOR logic gate into the output digital stream. Preferably, the two streams are preliminarily resynchronized by way of a first pair of flip-flops, timed by the clock signal, before effecting the sampling with the two diversely delayed clock signals.
According to another aspect of the invention, a circuit is provided for delaying each transition that immediately follows a preceding transition in a digital stream of input data. The circuit comprises a control circuit including at least a pair of propagation paths of a digital stream of input data, each path having an output bistable switch timed by a clock signal. The output bistable switch of a first path outputs a first digital stream of transitions nonsuccessive to another transition, and the output bistable switch of the other path outputs a second digital stream of transitions successive to another transition.
The circuit further comprises a delay circuit including at least an output XOR logic gate receiving the first and second digital streams whose transitions are independently delayed by different time intervals such that the difference is equal to a prefixed time interval, through respective inputs. The delay circuit outputs a recombined digital stream of selectively delayed data identical to the data of the input stream. The bistable output switches of the two propagation paths of the control circuit may be flip-flops synchronized by the clock signal and the paths may optionally comprise resynchronizing input flip-flops and a combinatory logic circuit identifying first transitions not immediately following a preceding transition and second transitions immediately following a preceding transition. Such a logic circuit may include an XOR layer, an AND layer and another XOR layer.
Since the transitions so discriminated of one of the two streams of each pair of propagation paths may be delayed with respect to the transitions of the other stream, of a certain freely programmable time interval, the delay and reconfirmation block of the circuit of the invention allows for the introduction of delays even greater than a half period of clock signal, without causing any write error on the storage support.
According to a particularly favorable aspect of the present invention, the control circuit and the delay and recombination circuit may comprise multiple sets of components arranged in a tree-like structure and reciprocally connected by way of a plurality of pairs of propagation paths. In this way and by feeding several distinct input digital streams of fractional clock frequencies, the circuits may function at a reduced (fractional) clock frequency. Therefore, even the most critical parts in terms of speed requirements, as for example the control circuit (discrimination between the two types of transitions), may be realized in CMOS technology with attendant advantages in terms of simplicity of the design and reduced costs.
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Che, “Nonlinearity Measurements and Write Precompensation Studies for a PRML Recording Channel”, IEEE Transactions on Magnetics, vol. 31, No. 6, Nov. 1995.
Bollati Giacomino
Bruccoleri Melchiorre
Demicheli Marco
Malfa Maurizio
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Galanthay Theodore E.
Nguyen Linh
STMicroelectronics S.r.l.
Tran Toan
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