Image analysis – Image compression or coding – Including details of decompression
Reexamination Certificate
1999-08-03
2003-12-02
Mehta, Bhavesh M. (Department: 2625)
Image analysis
Image compression or coding
Including details of decompression
C382S107000, C382S235000, C382S236000, C382S244000, C375S240010, C375S240160
Reexamination Certificate
active
06658154
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of and a device for decoding a moving picture.
2. Description of the Related Art
In a device for decoding a moving picture, in order to simplify the structure, a plurality of processing parts are connected to one memory bus and a memory is connected to the memory bus by way of a memory control part. In the memory, coded image data, decoded image data, user data and audio data are stored. As a memory, while an ordinary DRAM may be employed, a synchronous DRAM such as a Rambus DRAM is usually employed in order to enable a higher speed access.
In a device for decoding a moving picture, it is only required that decoding processing of one frame is performed in a frame period, for example, {fraction (1/30)} sec of a coded video signal.
However, since a compression factor of coded data and a predictive method are different according to a picture, a coded data volume and a processing time for decoding the data are also different according to a picture.
Therefore, small buffer memories are respectively equipped to the plurality of processing parts and arbitration among bus rights is performed in the memory control part on accepting interrupt requests from the processing parts.
However, since a coded data volume and a processing time for decoding the data are different according to a picture, interrupt requests become competitive, so that a memory access efficiency is deteriorated owing to a synchronous DRAM being used in a random access manner. Hence, there arises a necessity to raise an overall performance of a hard ware, which becomes a cause for cost increase.
Further, although a simulation is generally performed in LSI design in order to shorten a development time, it is hard to specify in what conditions a memory access request of the worst case will occur, which allows only a simulation in the assumable worst case. In addition, there arises a case where it takes several days to perform a design simulation on a bit stream for seconds.
Therefore, operation of an LSI is currently guaranteed, after an LSI is designed and fabricated, by executing a test on an actual product while inputting much bit streams thereto.
However, it is still unknown whether or not operation in the worst case is really guaranteed. Further, when desired operation of the LSI is not guaranteed in a test on an actual product, the design of the LSI has to be changed, and similar processing must be repeated. Therefore, a development time for the LSI is forced to be longer. In order to avoid such an inconvenience, to fabricate an LSI with a higher performance than necessary causes a cost rise.
SUMMARY OF THE INVENTION
Accordingly, it is an object to provide a method and device for decoding a moving picture which are good in access efficiency to a RAM.
It is another object to provide a method and device for decoding a moving picture for which a design to meet required specifications is easy to be achieved.
In the 1st aspect of the present invention, there is provided a device for decoding a moving picture wherein a plurality of buffer memory parts are connected between a plurality of respective processing parts and a memory bus and a RAM is connected through a memory control part to the memory bus, wherein the memory control part assigns time slots to the respective buffer memory parts cyclically and in each time slot, the memory control part controls access between the corresponding buffer memory part and the RAM.
Although an SRAM may be employed as a RAM, since a relative large capacity is needed, a DRAM which is high in storage density and low in cost is practical. Further, with an ordinary DRAM in use, a higher speed access is made possible than in a random access by changing a column address in a sequential manner while designating a raw address as in a page mode (high access efficiency), but a synchronous DRAM such as a Rambus DRAM in which a column address is changed in a sequential manner with a internal counter is preferable since a still higher speed access is realized.
With the above aspect of the present invention, since a sequential access is performed to a RAM in a time slot, an access efficiency to a RAM can be prevented from being reduced with an access right frequently changing.
Further, since time slots can be determined while assuming the worst case in which access to an RAM is the severest, design of a device for decoding a moving picture is easy to be effected.
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Kohiyama Kiyoshi
Otobe Yukio
Takahashi Hidenaga
Yoshitomi Koji
Fujitsu Limited
Kassa Yosef
Mehta Bhavesh M.
Staas & Halsey , LLP
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