Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Reexamination Certificate
2000-03-13
2004-08-17
Nguyen, Steven H. D (Department: 2738)
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
C370S503000, C375S362000, C375S371000
Reexamination Certificate
active
06778543
ABSTRACT:
The present invention concerns a method of controlling the synchronization in a data packet communication network having at least two serial communication buses (D, E) interconnected by a bridge and each defining successive time cycles each having a duration specific to the said bus under consideration, the said method having the following steps:
detection of a relative drift between the respective cycles of the said at least two serial communication buses,
transmission of a command for modifying the duration of the cycle of one of the said at least two serial communication buses.
Communication networks are known which are formed from a number of serial communication buses in accordance with the IEEE 1394 standard.
These buses are organized as a network, that is to say they are interconnected by items of interconnection equipment which are referred to as “bridges”.
The bridges connecting serial communication buses form more particularly the subject of the P1394.1 standard which is in the process of discussion.
A bridge is an item of equipment composed of two “portals” which makes it possible to interconnect two 1394 buses. A “portal” is a set of 1394 ports belonging to the same 1394 bus.
The bus network thus forms a structure with a tree hierarchy in which one of the buses is considered as the upper bus, referred to as the “root” bus, from which the various other buses constituting the branches of the structure with a tree hierarchy extend.
Each serial communication bus of such a network interconnects various peripherals such as printers, computers, servers, scanners, video recorders, decoders (known by the term “set top boxes”), televisions, digital cameras, video cameras, digital photographic equipment etc.
These peripherals are generally referred to as nodes.
On each serial communication bus of the network, each peripheral or node has an internal clock from which so-called clock pulses are generated at a so-called clock frequency, for example equal to 24.576 MHz.
On each serial communication bus of the network, one of the nodes is referred to as the “Cycle Master” and the “Cycle Master” node of the “root” bus is referred to as the “Net Cycle Master”.
Moreover, all “Cycle Master” nodes of the network have a characteristic which is specific to them, since it depends on the frequency of their internal clock, from which the duration of a “reference period” or “cycle” is defined.
The duration of the cycle denoted by T is equal to an integer number n
init
of dock pulses common or otherwise to all the buses and which is multiplied by the inverse of the frequency of the internal clock specific to the “Cycle Master” node.
The duration of the cycle T is thus for example equal to 125 microseconds.
When two serial communication buses are connected by a bridge, the “Cycle Master” of one of the buses must synchronize its cycles in relation to the cycles generated by the “Cycle Master” of the adjacent bus.
The “Net Cycle Master” node will then generate on the bus, every 125 microseconds, a so-called “cycle star” signal.
This signal intended for the other nodes of the bus informs them that they can send their isochronous data packet associated with each cycle of the bus under consideration, to one or more of the other buses which are connected to the said bus under consideration respectively by one or more bridges.
Furthermore, the specifications of the 1394 standard indicate that the internal clock frequency of a 1394 peripheral must be 24.576 MHz+/−100 ppm which allows, at maximum, a difference of two internal clock cycles every 3 cycles of the bus between two 1394 peripherals.
The maximum difference is in fact obtained when the internal clock frequency of one of the peripherals is 24.576 MHz+100 ppm and the other frequency of the other peripheral is 24.576 MHz−100 ppm.
For example, the frequency of the internal clock specific to the “Net Cycle Master” denoted by CM
A
has a value of 24.576 MHz+100 ppm, while that of the internal clock specific to the “Cycle Master” CM
B
of a lower level bus which is directly connected to the upper level bus by a bridge has a value of 24.576 MHz−50 ppm.
The communication networks formed from serial communication buses allow the transmission of packets synchronized from the cycles of the buses under consideration. The buses are for example used for transmitting audio/video type data packets in real time.
Thus, when the two “Cycle Masters” mentioned previously, denoted by CM
A
and CM
B
, are taken, with their respective clock frequency values, namely 24.576 MHz+100 ppm and 24.576 MHz−50 ppm, the durations of the cycles calculated for each of the said “Cycle Masters”, denoted respectively by T
A
and T
B
, are different on account of the different frequencies of the internal clocks specific to these “Cycle Masters”.
FIG. 1
moreover illustrates this phenomenon and shows, on two superposed axes, for one and the same integer number n
init
such that T
A
=n
init
/F
A
and T
B
=n
init
/F
B
, where F designates the dock frequency of the “Cycle Master” under consideration, a cycle of duration T
B
greater than the cycle T
A
.
In this figure there are depicted, above the first two cycles of the bus, the numbers of two data packets identified by the numbers
1
and
2
.
It should also be noted that the case depicted in
FIG. 1
is highly improbable in reality since it envisages a null phase displacement at the beginning of each of the first cycles of the two buses.
However, comparison of these two axes reveals a relative drift of the starts of each cycle which corresponds in fact to a change in the phase displacement (null at the time origin in the figure) over time between the cycles under consideration.
Furthermore, two arrows have been depicted between the two axes to indicate the delay with which the data packets denoted by
1
and
2
are transmitted on the bus B after having passed over the bridge interconnecting the buses A and B. It is estimated in effect that the delay depicted here is equivalent to two cycles and is explained by the time necessary for processing the packets in the bridge before their transmission on the bus B.
Thus, in view of the relative time drift noted between the respective cycles of the buses A and B, at the end of a certain number of cycles, a data packet coming from the bus A will not be transmitted at the bus B.
The non-transmission of this data packet therefore risks being highly detrimental for real time data of the audio and/or video type.
This is because, with data for example of video type, it is very important to transmit all the video data packets correctly in order not to degrade the video image obtained from the transmitted packets.
Generally, if it is noted that the duration T
A
is less than T
B
, then one data packet will be lost at the end of a certain number of cycles, which means that one cycle will have been lost and if, on the contrary, T
A
is greater than T
B
, then no data packet will be transmitted during one of the cycles and there will therefore be a cycle devoid of any significance, leading, through that very occurrence, to a loss of synchronization in the processing of audio and/or video type data in real time.
The detection of a relative drift between the cycles which will subsequently be responsible for a lost cycle or one cycle too many is carried out in each bridge, for a given cycle, by counting simultaneously, with the help of registers, the numbers of pulses generated by the clocks of the two buses under consideration and for example comparing these two numbers with one another at regular time intervals.
In order to remedy the drift problem, the P13941 standard makes provision, as soon as a drift is detected at the level of the bridge, to send, to the “Cycle Master” CM
B
, a message transmitting a command for modification in consequence of the integer number n
init
of dock pulses, in order to make the cycle durations T
A
and T
B
coincide.
It should be noted that this resynchronization is carried out only in pairs of buses.
By way of e
Accarie Jean-Paul
El Kolli Yacine Smail
Frouin Laurent
Tannhauser Falk
Canon Kabushiki Kaisha
Fitzpatrick ,Cella, Harper & Scinto
Nguyen Steven H. D
Stevens Roberta
LandOfFree
Method and device for controlling the synchronization... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and device for controlling the synchronization..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and device for controlling the synchronization... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3305537