Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Patent
1997-10-14
2000-05-02
Mai, Tan V.
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
G06F 700
Patent
active
060584114
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention pertains to the field of computing technology and microelectronics and is useful in producing high- speed integrated circuits and sets of integrated circuits for digital signal processing, for computing product sums, for multiplication and addition processes.
2. Description of the Related Art
The device for computing product sums is known, containing eight 2-bit input data bus, sixteen input buffer elements, four 2 -bit conveyer adders of the first layer, 4 blocks of results normalization of the first layer, two conveyor adders of the second layer, two blocks of results normalization of the second layer, output conveyor adder of the third layer, two intermediate flip-flops, output normalization block, two output buffer flip-flops, two output buffer elements, input of the main clocking signals, "end of word" input signal, control signal input, control block including shifter, two one-bit result outputs, each adder includes two output flip-flops, a carry flip-flop and combinational two-bit adder consisting of two combination 1-bit complete adders, input of the main clocking signal, "end of word" signal input, two one-bit outputs, each of normalization blocks of the first and second layer includes delay flip-flop, controlling "end of word" input, commutator, two one-bit inputs and two one-bit outputs, normalization block of the third layer includes one-bit charge inputs: "end of word" input, control signal input, two delay flip-flops, two commutators, And - No gate, control block shifter includes seven flip-flops, elements connections are organized in the order of their listing ([1], p. 107-125).
The described device realizes the principle (for case m=0): ##EQU1##
Here
However, the described device can't computing product sums of A.sub.i .times.2.sup.i- type or sums of partial products of a.sub.1.sup.x b.sub.j.sup.x 2.sup.i+j type and so can't be applied in multipliers.
The device for computing product sums is known, working in two modes: computation of partial product sums of two pairs of 8-bit numbers, computation of one pair of 16-bit numbers. The device is two-channel with processing of two bits in clock cycle in each channel.
The device includes four blocks of adders, six conversion circuits of the direct code into compliment, two full 2-bit adders with carry storage, two normalization blocks, sign digit circuit, control block, four output buffer flip-flops, clocking signal input, "end of word" character accompanying signal input, initial set signal input, working mode selection input, two 2-bit output data bus, each adder block includes seven 2-bit conveyor adders with carry storage, each device adder includes 5 flip-flops, two full 1-bit combinational adders, four one-bit inputs, two one-bit outputs, each circuit of the converter of the direct code into complement includes four flip-flops, two commutators, analysis circuit, four 1-bit inputs, two 1-bit outputs, the sign digit circuit includes six flip-flops, one EXCLUSIVE OR gate, four 1-bit data inputs, signal input of "end of word" character accompaning, five 1-bit outputs, each normalization block includes three flip-flops, one commutator, control strobe of character dump, two 1-bit inputs, two one-bit outputs, all elements are connected in the following sequence: four blocks of adder, four code converters, two adders, two normalization blocks, two code convertors, four input buffer flip-flops ([1], p. 54-84).
The device computes partial product sums of a.sub.i *b.sub.j type i.e. realizes the principle: ##EQU2##
Here
However the device doesn't form partial a.sub.i *b.sub.j products and so can't be complete functional block for multiplication.
The device for computing product sums is known, working in two modes; computing of 16-bit numbers products; computing of two product sums of 8-bit numbers. The device includes the above mentioned device as well as eight input buffer flip-flops, four 8-bit (two including four) working registers of reception and storage of input operands, two im
REFERENCES:
patent: 4215419 (1980-07-01), Majerski
patent: 5305250 (1994-04-01), Salam et al.
patent: 5602766 (1997-02-01), Bauer et al.
Khalidov Rashid Bakievich
Lancaster, Technologies, LLC.
Mai Tan V.
Shaihov Alisher Vahidovich
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