Pulse or digital communications – Bandwidth reduction or expansion
Reexamination Certificate
1998-11-20
2003-12-09
Ghebretinsae, Temesghen (Department: 2631)
Pulse or digital communications
Bandwidth reduction or expansion
C375S224000, C714S738000, C341S051000
Reexamination Certificate
active
06661839
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method of compressing a data to be compressed such as a test pattern used for testing, for example, a semiconductor integrated circuit (IC), a method of expanding such data, an apparatus for compressing such data, and an apparatus for expanding such data. In addition, the present invention relates to a compressing method, an expanding method, a compressing apparatus and an expanding apparatus for compressing and expanding a test pattern used for testing a large scale semiconductor integrated circuit (LSI) by each pin basis of a large scale semiconductor integrated circuit (hereinafter referred to as LSI).
BACKGROUND ART
In an IC testing apparatus (commonly called IC tester) for testing a semiconductor integrated circuit (hereinafter referred to as IC), the data quantity or volume of test patterns applied to an IC to be tested (IC under test) becomes extensive. Therefore, the extensive test pattern data are compressed to be transmitted and the compressed test pattern data are expanded at a receiving side to reconstruct original test pattern data which are applied to an IC under test. As a method for compressing test patterns or other extensive data, a Lempel Ziv's algorithm (LZ compressing method) which utilizes a dictionary, a Huffman's algorithm (Huffman compressing method) which utilizes statistical characteristics of the data, or variations of those various compressing methods have conventionally been used in a data compressing apparatus. Each of those compressing methods is a single compressing method and each of the data compressing apparatus applies this single compressing method to all the data to be compressed to perform the compression of those data.
However, since each data such as a test pattern has a uniform data type and is composed of a plurality of unit data sequences but a considerably different data structure or a statistical characteristic from each other, an efficient compression has not been possible depending on the data to be used. For example, when each of different portions within a same data is significantly different from each other in terms of the pattern structure or the statistical characteristic, a high compression efficiency can be obtainable for a certain portion but the compression efficiency becomes low for remaining portions. As a result, the compression rate is relatively low for the entire data. In addition, regarding the processing time, since the processing time is different depending on the structure of a data, an optimum processing time has not been attained.
There has been proposed, from this stand point, a data compression wherein a test pattern is divided into blocks each having a different data structure or a statistical characteristic from the others and an appropriate compressing method is applied to each block to compress the data.
However, since, in this data compressing method, the test pattern to be compressed is compressed in a block basis, it is required that the data expansion is also performed in a block basis. Therefore, it is impossible, in this compressing method, to expand the compressed test pattern in a real time basis.
Further, talking about the microprocessors produced by Intel Corporation as example, the number of pins has increased year by year as the integration degree is improved as seen in the models 4004 in 1971 having 16 pins, 80286 in 1982 having 68 pins, 80386 in 1985 having 132 pins, 80486 in 1989 having 168 pins, Pentium in 1993 having 296 pins, and Pentium Pro. in 1995 having 387 pins. As a result, an automatic IC test system (ATE) has also been shifted to a system wherein the hardware of a testing apparatus corresponds to a pin (per-pin system). This is because, with the per-pin architecture, the automatic IC testing system can flexibly cope with the increasing number of pins.
In order to solve the test pattern problems described above, there are required a per-pin compressing apparatus and a per-pin expanding apparatus wherein a test pattern is handled in the state that the test pattern is divided into a plurality of data each corresponding to a pin. The per-pin architecture has advantages such as (a) since the test data each corresponding to each pin can be down loaded into an internal memory of an automatic test system at the same time, the down loading time of a compressed test pattern can be reduced, (b) since management of the compressing apparatus and the expanding apparatus is simplified, the automatic test system can flexibly cope with increase of the number of pins of an IC.
A conventional automatic IC testing system (hereinafter referred to as ATE) holds therein a test pattern for testing an IC in a pattern generator. Therefore, in the ATE, a very long time is required for down loading a test pattern from a disk drive storing the test pattern therein to a pattern generator of the ATE. For example, approximately one hour is required, in case of a down loading via a network, for down loading a test pattern having approximately one (1) G bytes (giga bytes). Therefore, it is a serious problem to be solved to decrease the down loading time and to improve an availability factor of the ATE.
DISCLOSURE OF THE INVENTION
It is an object of the present invention to provide a data compressing method wherein the data to be compressed having data portions, which are called hereinafter as unit data sequences and each of which has a different structure or a different statistical characteristic is divided into the unit data sequences which are distributed into a plurality of blocks each corresponding to one of those factors of data structure and structural characteristics of data and the unit data sequences distributed to the respective blocks can efficiently be compressed by applying optimum compressing methods to the respective blocks.
It is another object of the present invention to provide a data expanding method wherein the respective data sequences divided into a plurality of blocks and compressed can be expanded and reconstructed to the original data without any information loss.
It is still another object of the present invention to provide a test pattern compressing method and a test pattern compressing apparatus wherein a test pattern is divided into test sequences each corresponding to each pin of a semiconductor integrated circuit and the test pattern to be compressed can efficiently be compressed by measuring the structure or the statistical characteristic of the data to apply an optimum compressing method to each test sequence.
It is still another object of the present invention to provide a test pattern expanding method and a test pattern expanding apparatus wherein respective test sequences for each pin of a semiconductor integrated circuit compressed by the above compressing method or compressing apparatus can be expanded to the original test pattern data in real time basis for each pin without any information loss.
It is yet still another object of the present invention to provide a test pattern compressing method and a test pattern expanding method wherein data sequences divided into a plurality of blocks is compressed by applying an optimum compressing method to each of the blocks and the compressed data divided into those plurality of blocks can be reconstructed to the original data from the respective blocks without any information loss.
It is yet still another object of the present invention to provide an automatic test system of a semiconductor integrated circuit wherein a down loading time of a test pattern is reduced using the test pattern compressing apparatus and/or the test pattern expanding apparatus.
The data compressing method according to the present invention is characterized in that in a compressing method wherein an input data having a redundancy, for example, a test pattern data, is divided into test sequences and compressed in each pin basis of a semiconductor integrated circuit, the data compressing method comprises the steps of: dividing each input data into a plurality of data portions, namely unit data seq
Ishida Masahiro
Tilgner Marco
Yamaguchi Takahiro
Advantest Corporation
Gallagher & Lathrop
Ghebretinsae Temesghen
Lathrop, Esq. David N.
LandOfFree
Method and device for compressing and expanding data pattern does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and device for compressing and expanding data pattern, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and device for compressing and expanding data pattern will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3163476