Pulse or digital communications – Receivers – Interference or noise reduction
Reexamination Certificate
2000-07-17
2004-04-13
Vo, Don N. (Department: 2631)
Pulse or digital communications
Receivers
Interference or noise reduction
C375S355000
Reexamination Certificate
active
06721375
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method and an arrangement for compensation of phase delays[, as generically defined by the preambles to claims 1 and 8, respectively].
In numerous technical applications, there is a need for converting an analog sensor signal into a digital signal. Because of the individual members of a signal detection chain used for this purpose, delays occur between the original analog signal and the digital signal that is to be further processed.
From German Patent Disclosure DE-OS 195 14 410, a device for detecting a pulsating variable is known, in which, to assure that a signal without oscillation would be obtained, an electronic filter is provided, which is constructed as an analog circuit and has at least one first member for differentiation and delay and one second member for multiplication of the differentiated and delayed signal, as well as a subtraction stage, in which the filtered signal can be subtracted from the unfiltered signal in order to generate a smoothed output signal. The object of this reference is to smooth a pulsating input signal; it does not address signal errors that occur from phase delays in a signal detection chain for converting a digital signal into an analog signal.
SUMMARY OF THE INVENTION
The object of the invention is a compensation, to be done in a simple way, that is, at the least possible expense for circuitry, of phase delays which occur in discrete-time sampling of an analog output signal and which lead to an error in the sampled digital signal.
According to the invention, effective, easy to achieve compensation of phase delays that occur in discrete-time sampling of an analog output signal is now made available. Phase delays that result from signal processing by an anti-aliasing filter as well as a sampling member are compensated for according to the invention in reverse order of their creation.
Expediently, the case of a further phase delay of the sampling signal, caused by an idle time, in particular an idle time which occurs in further processing of the sampling signal and by which an idle-time-delayed sampling signal is generated, a compensation of the phase delay of the sampling signal, caused by the idle time, is performed taking into account the idle time and the sampling period of the sampling member, to obtain an idle-time-compensated sampling signal, and the idle-time-compensated sampling signal is subjected to the phase shift compensations of claim 1 for the sake of further phase compensation. Thus in an effective, phase delays which occur between the sampling of the signal and its re-use (for instance in a regulator or in a correction function), can be compensated for.
Expediently, a phase delay caused by the sampling member, which delay can be represented by the equation
ϕ
A
=
ω
·
1
2
·
T
A
=
-
2
·
π
·
f
·
T
A
2
-
π
·
f
·
T
A
in which f is the signal frequency and T
A
is the sampling period of the sampling member, is corrected by means of a linear extrapolation using a correction value of the form −Y
k,2
=X
k
+½·(x
k
−x
k−1
), in which x
k−1
, x
k
are values of the sampling signal in successive sampling periods T
T,k−1
, T
T,k
. This correction can be performed by computer at relatively little effort or expense and represents a very good compensation for typical phase delays that occur in sampling members.
Expediently as well, a phase delay which is caused by the anti-aliasing filter and can be represented in the form &phgr;
F
=−arctan(2·&pgr;·f·T
F
), in which T
F
is the filter time constant of the anti-aliasing filter, is corrected by a correction value of the form y
k,3
=x
k
+T
F
/T
A
·(x
k
−x
k−1
). This correction can also be performed inexpensively, and compensates with sufficient accuracy for a phase delay caused by an anti-aliasing filter.
In an advantageous embodiment of the invention, furthermore, a phase delay which is caused by the idle time T
T
and can be represented in the form &phgr;
V
=−arctan(2&pgr;fT
F
)−&pgr;fT
A
−2&pgr;fT
T
is corrected by a correction value of the form
y
k
,
1
=
x
k
(
1
+
T
T
T
A
)
-
x
k
-
1
·
T
T
T
A
This clearly means that the error occurring during the idle time T
T
is imposed on the sampling signal with an inverse sign in the next sampling step and thus is corrected. This compensation likewise furnishes good correction results and can be performed in a simple way.
Expediently, the individual phase delay compensations are performed successively, so that in all, for correcting a sampling signal during one sampling period, sampling signals of two or three preceding sampling periods are taken into account.
It proves to be advantageous that the individual phase delay compensations perform in reverse order from the order in which they occurred, so that partly compensated signals are also available.
In a preferred embodiment of the arrangement according to the invention for compensation for phase delays, the means for compensation of the phase delay caused by the sampling member, the anti-aliasing filter, or the further processing idle time, each have three parallel signal transmission channels, in which a first signal transmission channel serves to transmit an unaltered sampling signal; a second signal transmission channel, having a multiplier member, serves to transmit a sampling signal multiplied by a factor, and a third signal transmission channel, having a delay member and a multiplier member, serves to transmit a sampling signal, delayed by one sampling period and multiplied by a factor, to a summation member.
It proves to be expedient that the means for compensation of the phase delay caused by the sampling member, the anti-aliasing filter, or the further processing idle time, are connected in series with one another in such a way that in all, a phase-compensated output signal U
S,K
is obtained, taking into account the uncompensated sampling signals of the preceding three sampling periods.
In a further preferred embodied of the arrangement of the invention, this arrangement has three series-connected delay members z
−1
, multiplier members connected to them and parallel to one another, and a summation member for adding the output signals of the multiplier members to achieve a phase compensation for obtaining a phase-compensated sampling signal U
S,K
of the form
U
S,K
(
k
)=
A·U
T
(
k
)+
B·U
T
(
k
−1)+
C·U
T
(
k
−2)+
D·U
T
(
k
−3)
in which U
T
(k−i), where i=0, 1, 2, 3, represents the uncompensated sampling signal U
T
delayed by i sampling periods, and A, B, C, D are system constants of the signal sampling path. Thus at little computational effort, it is possible to achieve the phase compensation of the invention, since the system constants A, B, C, D are predeterminable and do not have to be regularly re-calculated.
In a further preferred feature of the arrangement of the invention, this arrangement has means for turning off the phase compensation in the event that a change in the input signal within one sampling period exceeds a threshold value. As a result, severe fluctuations in the compensated signal in the event of very fast signal changes at the input to the compensation can effectively be prevented.
REFERENCES:
patent: 4694414 (1987-09-01), Christopher
patent: 5787387 (1998-07-01), Aguilar
patent: 5815580 (1998-09-01), Craven et al.
patent: 5841811 (1998-11-01), Song
patent: 2002/0114270 (2002-08-01), Pierzga et al.
patent: 195 14 410 (1996-10-01), None
patent: 98 23037 (1998-05-01), None
Robert & Bosch GmbH
Striker Michael J.
Vo Don N.
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