Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2003-03-05
2004-08-17
Lam, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185200, C365S189070
Reexamination Certificate
active
06778440
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuit memory devices, and more particularly, to nonvolatile memories such as an electrically programmable read only memory (EPROM), an electrically erasable and programmable read only memory (EEPROM) and a FLASH EEPROM that is erasable by groups of memory cells. In these non-volatile memories, the present invention concerns a method and device for controlling a group of memory cells to check whether they are all in the same electrical state.
BACKGROUND OF THE INVENTION
In non-volatile memories, it is necessary to check whether a group of memory cells are all in the same electrical state. This check is necessary in many circumstances, for instance, in memory manufacturing test operations or during use of the memory in an electronic system such as a microprocessor.
At present, such a check is carried out cell by cell by selecting each cell in a readout mode and comparing the read signal with a reference signal supplied by a reference cell. The reference cell which is identical to the memory cell. This checking process is time consuming and labor intensive.
SUMMARY OF THE INVENTION
In view of the foregoing background, an object of the present invention is to quickly check the electrical state of memory cells in an integrated circuit memory.
This and other objects, advantages and features in accordance with the present invention are provided by simultaneously reading the memory cells in groups of N cells, summing the N read signals and comparing their sum to a reference signal supplied by a reference cell for determining whether the N memory cells of the group are in the same electrical state.
One aspect of the invention is directed to a method of simultaneously checking the electrical state of a group of N memory cells in a non-volatile type memory, where each cell of the memory can take on a first electrical state or a second electrical state.
The memory further comprises at least one memory cell, designated a checking cell, which is in the second electrical state but exhibits a readout characteristic curve that is modified relative to the other cells of the memory.
The method preferably comprises simultaneously selecting in readout the N memory cells to check as well as the checking cell, and summing the N read signals to obtain a summed signal. The summed signal is compared with the signal read on the checking cell to provide a given state signal when the summed signal is less than the signal read on the checking cell. This indicates that the N memory cells are in the first electrical state. If another state signal is given, this indicates that at least one memory cell is not in the first electrical state when the summed signal is greater than the signal read on the checking cell.
Another aspect of the invention is directed to a device for simultaneously checking the electrical state of a group of N memory cells in a non-volatile type memory, where each memory cell can take on a first electrical state or a second electrical state.
The memory device preferably further comprises at least one memory cell, designated a checking cell, which is in the second electrical state but exhibits a readout characteristic curve that is modified relative to the other cells of the memory. The memory device also comprises means for simultaneously selecting in readout the N memory cells to check, as well as the checking cell.
The memory device preferably further comprises means for summing the N signals read in the N memory cells to obtain a summed signal, and comparison means for comparing the summed signal with the signal read in the checking cell. The comparison means supplies a first state signal when the N memory cells are all in the same above-mentioned electrical state, and a second state signal when just one memory cell among N is in the second electrical state.
REFERENCES:
patent: 5886925 (1999-03-01), Campardo et al.
Aitouarab Leila Sedjai
Fournel Richard
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Jorgenson Lisa K.
Lam David
STMicroelectronics SA
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