Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor
Reexamination Certificate
2000-03-13
2003-01-28
Sherry, Michael (Department: 2829)
Electricity: measuring and testing
Measuring, testing, or sensing electricity, per se
With rotor
C324S754090, C324S758010
Reexamination Certificate
active
06512362
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of and a device for pulsed high-current loading of integrated circuits and structures.
BACKGROUND OF THE INVENTION
One of the main causes of failure of integrated circuits are electrostatic discharges (ESD) during which the discharge current flows through the integrated circuit. Together with electric overstress (EOS), which is difficult to distinguished therefrom, they account for approximately 50% of the cases of field failure. External capacitors such as the human body or even the component as such (charged device) including the integrated circuit inside come into question as ESD charge sources. Charging is produced by friction (tribologic electricity) or by induction and contact in the electro-static field.
For protection of the integrated circuits protective structures are used on their inputs and outputs. These protective structures are intended, on the one hand, to take no influence on the functional integrity of the circuit, but, on the other hand, in the case of discharge they should branch off high currents along reliable paths around the core of the circuitry or out thereof, limiting the voltages to values which are not critical for the interior (e.g. gate oxides) of the circuit. For the synthesis of such a protective concept it is of vital importance to know the characteristics of these structures precisely within the pertinent current and time ranges.
Moreover, for the industrial product qualification the efficiency of such a protective concept must be verified and quantified in view of the electrostatic loads occurring in real operation. The qualification must be performed separately by housing types. To this end, characteristic load models such as the Human Body Model (HBM) and the Charged Device Model (CDM) with their derivatives have been defined. These models are substantially distinguished from each other by their current and time ranges. On account of the definition of a 1.5 k serial resistor and a 100 pF capacitor the Human Body Model presents a double exponential current development increasing within the range from up to 10 ns to approximately 0.66 A/kV precharging voltage and flowing via two terminals of the integrated circuit, By contrast, the capacitance of CDM discharge is defined only by the component as such or by its conductive elements relative to its environment. As the chip and housing area increases, this capacitance also increases due to the increasing number of pins (>300) and the reduction of the thickness of the housing. The risk of ESD commences when the terminals are separated after the chip has been pressed in the plastic housing, and still persists even after its assembly in a printed circuit board. As a result of ever-increasing automation, the probability of a load according to the Charged Device Model increases as well. The CDM model excels itself not only by the exchange of charges via an individual terminal of the circuit, but also by its very high currents of up to several Ampere, which are limited only by the terminal inductance and the sparking resistance and which are reached within fractions of a nano second.
Due to the high current, high voltage drops by several 10V may be established across the protective structures and supply lines, which become an imminent danger for the even thinner gate oxides, even when the protective structure responds at the sufficient rate. As the distance of the breakdown voltage from the gate oxides and pn junctions for protection and for more complex supply bus systems increases, the imminent risk continues rising which is involved by the extremely short high-intensity pulses of the CDM.
The quantification of the electrostatic load-bearing capacity is therefore realized in ESD testers in which the different loading models are implemented. Protective elements and integrated structures in the high-current range can be characterized by means of rectangular pulses which are, as a rule, generated by the discharge of lines and which are applied to the two terminals of a protective element.
The ESD load-bearing capability of integrated circuits in correspondence with the CDM model has so far been quantified in testers which are distinguished from each other by the type of the discharge contact, by the type of the device mounts, and by the charging principle. The standardization of the testing method has been and is strongly impeded by substantial correlation problems. One cause is the complex interactions among the integrated circuit, its housing, the test adapter and the testing device as such, which occur during the very short pulses. These interactions take an influence first on the discharge current and second on the effects which this current produces on the circuit. A key problem is the pulse measuring technique which is insufficient for the individual current increases (<100 ps) of so steep a slope.
Among the known CDM testers a distinction is made among the following types:
(1) Non-Contact, Non-Socketed (NN)
The charged component is placed in a rear position on a grounded conductive support. For loading, a grounded low-inductance electrode is attached to the component terminal to be loaded. The discharge then takes place in dependence on the field intensity and the ignition conditions by sparks or metal contact. This technique, however, displays a bad reproducibility of the current development in the case of pre-charging voltages higher than 1 kV. Moreover, with vertically arranged (DIL), the contact is not reliable for very small or even bent terminals. Further uncertainties arise as a result of mechanical-electrical spring contacts. The mechanical positioning permits only a very slow test sequence. The insufficient bandwidth of the available pulse measuring technique creates additional problems. The sensitive HF cables and connectors, which are required for discharge current measurement, may prematurely age and falsify the test result in view of frequent re-positioning during the test.
(2) Contact, Non-Socketed (CN)
The charged component is placed in a rear position on a grounded conductive support. An opened relays connects the charged device to the ground of the tester. A relay is closed for loading.
In this method, however, only a decelerated low-amplitude discharge occurs as a consequence of the relay and its inductance. The method displays a bad reproducibility of the current development in the case of pre-charging voltages higher than 1 kV by spark discharge. Moreover, the contact is unreliable in the case of very small or even bent terminals. The mechanical positioning permits only a slow test sequence. The measuring technique of this method can be mapped on the technique of the “nn” type only conditionally.
(3) Non-Contact, Socketed (NS)
The component is arranged on a test mount, possibly a test adapter, or a printed circuit board to increase the spacings between the terminals. The test amount in its entirety, inclusive of all lines provided thereon, is charged relative to the testing system. For loading, one terminal is contacted by attaching two contacts under atmospheric conditions. The mount and board capacitance (background capacitance) present behind the component is discharged via this terminal. In this method a complex system of lines and line termination resistors determine the complex discharge current shape and, in combination with the integrated circuit, may result in unforeseeable effects. As significant pulse measuring methods are lacking, the result can only be transferred to other systems or to another type with difficulties or not all. Another disadvantage resides in the aspect that background capacitance taking an influence on the fail voltage and the physical failure signature increases the accumulated energy.
(4) Contact, Socketed (CS)
The component is disposed in a test mount, possibly a test adapter, or a printed circuit board to increase the spacings between the terminals. The test mount in its entirety, inclusive of all lines provided thereon, is charged relative to the testing system. For lo
Fraunhofer Gesellschaft zur Foerderung der angewandten Forschung
Kaminski Jeffri A.
Kinberg Robert
Nguyen Trung
Sherry Michael
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