Method and device for avoiding latent errors in a logic network

Details Method and device for avoiding latent errors in a logic network Method and device for avoiding latent errors in a logic network

1990-04-18

1992-08-18

Smith, Jerry

Excavating

371 81, 307464, 307441, G06F 1118

Patent

active

051405946

ABSTRACT:
A method for avoiding latent errors in a logic network for majority selection of binary signals in a triplicated system. Errors which result from errors or faults in one of two or more parallel-connected transistors of one or more separate logic devices included in the logic network are avoided by repeatedly switching each of the separate logic devices in a manner such that transistors which were parallel-connected become series-connected, and vice versa. As a result, these devices will perform alternately logic operations which are the dual correspondence of one another, e.g. NAND- and NOR-operations with the aid of the same transistors (61-66) in both instances. Thus, in practice, majority selection will be performed alternately with two mutually different logic networks, which are the dual correspondence of each other.

REFERENCES:
patent: 4355683 (1982-10-01), Griffiths
patent: 4468574 (1984-08-01), Engeler et al.
patent: 4555721 (1985-11-01), Bansal et al.
patent: 4583224 (1986-04-01), Ishii et al.
patent: 4617475 (1986-10-01), Reinschmidt

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