Method and device for automatic simulation verification

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system

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703 14, 703 17, 703 20, 703 21, 714 25, 714 33, 714736, G06G 762, G06F 1750

Patent

active

061310794

ABSTRACT:
A method and device for automatically verifying results of a simulation is disclosed. External stimuli are applied to a device under test and observed output is generated in response thereto. The observed output is applied to a non-cycle accurate model of the device comprising procedures which simulate significant events corresponding to the significant events of the observed output. Verification conditions are set according to the aspects of the device under test which are being tested and the verification conditions are applied to the output from the non-cycle accurate model. The verification conditions are associated with a procedure of the model such that the verification condition is verified before or after execution of the procedure. In addition, the verification conditions may be executed at the end of the simulation to ensure that all events which should have occur, have occurred. It is possible to control which observed outputs are applied to the model so that a user can interactively observe changes in the state of the model. If a verification condition is not satisfied, an error flag is raised marking a part of the model output which did not satisfy a verification condition.

REFERENCES:
patent: 5428766 (1995-06-01), Seaman
patent: 5617430 (1997-04-01), Angelotti et al.
patent: 5808919 (1998-09-01), Preist et al.
patent: 5922079 (1999-07-01), Booth et al.
Amato et al, "Checking Linked Data Structures", IEEE Twenty-Fourth International Symposium on Fault-Tolerant Computing, 1994, pp. 164-173, Jun. 1994.

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