Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2006-09-19
2006-09-19
Crane, Sara (Department: 2811)
Semiconductor device manufacturing: process
With measuring or testing
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07109047
ABSTRACT:
A method of analyzing a circuit comprising a plurality of interconnects is disclosed herein. The method may comprise analyzing at least one electrical property associated with a first interconnect, wherein the first interconnect has at least one first physical dimension. The electrical property may then be stored. A second interconnect having the at least one first physical dimension may then be located and the at least one electrical property is applied to the second interconnect.
REFERENCES:
patent: 5999726 (1999-12-01), Ho
patent: 6013536 (2000-01-01), Nowak et al.
patent: 6266802 (2001-07-01), Malm et al.
patent: 6887791 (2005-05-01), Jung
McHardy Alex
Wang Yong V.
Crane Sara
Hewlett--Packard Development Company, L.P.
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