Method and device for analogue to digital conversion

Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion

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341159, 341172, H03M 112

Patent

active

061605085

ABSTRACT:
A parallel SC ADC (switched capacitor analog-to-digital converter) includes a passive sampling technique controlled by a global clock phase to reduce the influence of the sampling phase skew. Since it does not require operational amplifiers for sampling, it is very suitable for high speed applications, and yet it can reduce the sampling-phase-skew-related distortion by 20-40 dB in a high speed, parallel SC ADC.

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Jenq, Yih-Chyun, "Digital Spectra of Nonuniformly Sampled Signals: Fundamentals and High Speed Waveform Digitizers", IEEE T. Instrumentation and measurement, vol. 37, No. 2, pp. 245-251, Jun. 1988.
Conroy, et al., "An 8-b MS/s Parallel Pipeline A/D Converter in 1-.mu.m CMOS", IEEE J. Solid State Circuits, vol. 28, No. 4, pp. 447-454, Apr. 1993.

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