Pulse or digital communications – Synchronizers
Reexamination Certificate
1999-03-15
2002-07-23
Deppe, Betsy L. (Department: 2634)
Pulse or digital communications
Synchronizers
C327S151000, C327S160000
Reexamination Certificate
active
06424687
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to synchronization of digital data formed by sampling analog signals and transmitted on a digital interface from the sampling device to a receiving and converting device. More particularly this invention relates to methods and devices that eliminate data “overrun” or “underrun” due to differences in the sampling times of the sampling device and receiving and converting device.
2. Description of the Related Art
To understand the problem solved by this invention, refer now to FIG.
1
. An analog electrical signal
100
is created by a transducer such as a microphone in response to a physical phenomenon. The analog electrical signal is the input to an analog-to-digital converter (ADC) circuit
105
. At periodic conversion times established by the timing signal CLK
IN
115
, the ADC circuit
105
have an output digital signal
110
indicating the magnitude of the analog electrical signal at each of the periodic conversion times. The output digital signal
110
is then transferred to a transmitter
120
for transmission on a communication link
125
. The communication link may be a telephone connection or any other known digital communication protocol.
Often digital communication protocols divide the output digital signal
110
into frames or blocks for transmission on the communication link
125
. Plots
200
and
205
respectively of
FIGS. 2
a
and
2
b
show a single frame of data consisting in this instance of 32 digitized samples of the analog signal. Depending on the digital communication protocol each frame of the digitized samples has a header and trailer (not shown) appended respectively to the frame of the digitized samples. The header and trailer contain information such as timing, error detection cods, source and destination codes, and beginning and ending of transmission codes.
The header and trailer information is appended in the transmitter
120
and removed in the receiver circuit
130
after receiving the frame of the digitized samples.
The received digitized samples
140
are then transferred to a digital-to-analog converter (DAC) circuit
145
. The DAC circuit converts the received digitized samples
140
to an analog output signal
150
. The analog output signal
150
is used to drive an output transducer such as a speaker to convert the analog output signal
150
to a physical phenomenon.
The receiver circuit
130
and DAC circuit
145
are each synchronized by the timing signal CLK
OUT
135
. For a communication network as shown in
FIG. 1
to operate error free, the timing signals CLK
IN
115
and CLK
OUT
135
should have equal frequencies or periods. In practice, this is not feasible.
FIGS. 2
b
and
2
d
show two timing signals that have slightly different frequencies. The timing signal
205
has a lower frequency or a longer period than the timing signal
215
. This forces the frame length of plot
205
of
FIG. 2
b
to be longer than that of plot
215
of
FIG. 2
d
. Further, values of the magnitudes of the digitized samples will be in error as shown in plots
200
and
205
respectively of
FIGS. 2
a
and
2
b.
FIG. 3
a
illustrates the instance where timing signal of the CLK
IN
115
has a longer period or lower frequency than that of the timing signal CLK
OUT
135
. The amplitude Y
IN
310
is the value of the input sample D
2
300
. If the frequency of the input timing signal CLK
IN
115
were the same as the output timing signal CLK
OUT
135
, the amplitude Y
OUT
305
is the value that the sample D
2
315
should have to produce the analog output signal
150
of FIG.
1
.
Alternatively,
FIG. 3
b
illustrates the instance where input timing signal of the CLK
IN
115
has a shorter period or higher frequency than the output timing signal CLK
OUT
135
. As in the case of
FIG. 3
a
, the amplitude Y
IN
310
is the value of the input sample D
2
300
. As described in
FIG. 3
a
, if the frequency of the output timing signal CLK
IN
115
were the same as the output timing signal CLK
OUT
135
, the amplitude Y
OUT
305
is the value that the sample D
2
315
should have to reproduce the analog signal
150
of FIG.
1
.
Referring back to
FIGS. 2
a
to
2
d
, if the input timing signal CLK
IN
115
of
FIG. 1
has a lower frequency as shown in plot
205
of
FIG. 2
b
than the output timing signal CLK
OUT
135
of
FIG. 1
as shown in plot
215
of
FIG. 2
d
, the receiver
130
will sample the output digital data that is shown in plot
200
of
FIG. 2
a
. Since there are fewer samples of the output digital data
130
than expected during the period of one frame of the output timing signal
215
, there will be an overrun of the digital data. The output timing signal
215
will receive multiple copies of samples for the output digital data
140
causing extreme distortion in the analog output signal
150
.
Conversely, if the input timing signal CLK
IN
115
has a higher frequency as shown in plot
215
of
FIG. 2
d
than the output timing signal CLK
OUT
135
as shown in plot
205
of
FIG. 2
b
, the receiver
130
will sample the output digital data that is shown in plot
210
of
FIG. 2
c
. Since there are now more samples of the output digital data
130
than expected during the period of one frame of the output timing signal
205
, there will be an underrun of the digital data. The output timing signal
205
will miss capturing some of the samples of the output digital data
140
. This again caused extreme distortion in the analog output signal
150
.
Typically, the output timing signal
135
is synchronized to the transitions of the output digital data
110
employing a phase locked oscillator similar to those described in U.S. Pat. No. 5,577,080 (Sakaue et al.), U.S. Pat. No. 5,790,615 (Beale et al.), U.S. Pat. No. 5,652,532 (Yamaguchi), and U.S. Pat. No. 4,855,683 (Troudet et al.).
Sakaue et al. describes a digital phase-locked loop (DPLL) circuit, which achieves a high-precise phase matching between input and output clocks at high speed, irrespective of phase difference between both. The DPLL has a phase comparator for sequentially comparing an input clock with an output clock in phase and outputting phase comparison result signals. The DPLL has a random walk filter for sequentially adding and accumulating the comparison result signals inputted by the phase comparator, discriminating a relative magnitude between the obtained addition data and threshold value information, and outputting a frequency change signal corresponding to the discriminated result and the phase shift amount information. The DPLL further has a variable frequency oscillator for generating the output clock according to the frequency change signal, and a filter coefficient generating circuit for changing and outputting at least one of the outputted threshold value information and the phase shift amount information according to the phase synchronous status supplied from an operation status detecting circuit.
Beale et al. teaches a digital phase-lock loop network that provides input and output clock signals to a to a data buffer contained in digital data receiving system. The digital phase-lock loop network provides bit clock synchronization using a fixed input clock and an output clock having a variable frequency that is adjusted to correspond to the average input rate of the data samples into the data buffer. The digital phase-lock loop network allows the data buffer to be operated as a temporary storage device maintaining a nominal number of data samples therein at all times by avoiding any overflow and underflow data handling conditions that may otherwise cause loss of data. The digital phase-lock loop network of Beale et al. is particularly suited for the Eureka-147 system, which has become a worldwide standard for digital audio broadcasting (DAB) technology.
Yamaguchi sets forth a frequency difference detection circuit capable of increasing the detection sensitivity for a frequency difference and shortening the frequency difference detection time. The frequency difference detection circuit compr
Tian Wenshun
Yong Kah
Cirrus Logic Inc.
Deppe Betsy L.
George O. Saile & Assoc.
Lin, Esq. Steven
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