Method and device for addressable failure site test structure

Details Method and device for addressable failure site test structure Method and device for addressable failure site test structure

2001-01-05

2003-06-10

Nguyen, Vinh P. (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

Reexamination Certificate

active

06577149

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor processing, and more particularly, to a method and device for finding defects in a semiconductor process by using addressable test structure.
2. Background Information
Yield improvement is an important task in semiconductor processing. When a wafer is processed, it typically comprises hundreds of chips, or devices, that are later packaged into individual integrated circuits. After a wafer is manufactured, the wafer is examined to determine the location and types of defects. Either optical inspection of the wafer or electrical testing of the circuits on the wafer may be conducted. The defect patterns are compared with a reference set of defect patterns to identify the failure modes, and then the manufacturing process or equipment associated with those failure modes are adjusted to eliminate the cause of defects and improve yield rate.
In order to determine whether the defects on a wafer match a certain failure mode defect pattern, it is important to know the location of the defects on a wafer. Optical inspection provides an easy method to determine the location of defects caused by particles that have fallen on the wafer. However, not all particles on a wafer cause defects, as when particles fall on non-active regions. Moreover, some defects occur in the buried layers, and cannot be found by optical inspection. Thus, electrical tests are necessary to more thoroughly and accurately determine the existence and location of the defects. The electrical tests may be conducted by simply determining whether the circuitry is functional or defective. By mapping the location of the defective chips on a wafer, the failure modes can be determined and the processing steps may be improved accordingly.
The cause of defects can be more accurately diagnosed if the location of the defects within the chip can be determined. Such information can be used to generate a more detailed wafer defect map. Traditionally, the location of defects within a chip can be determined if the chip is a memory device, such as a RAM chip, a ROM chip, a flash memory chip, etc. Each memory cell within the memory chip has a unique address, and the corresponding location of a cell for each address is predetermined. Thus, the location of defects can be easily determined by testing the functionality of individual cells and mapping the location of the defective cells according to their addresses. However, such a method for determining the location of defects cannot be used for chips other than memory devices, such as logic circuit chips. Unlike memory cells, the logic gates on a logic circuit chip do not have addresses, thus there is no simple method of determining the location of defects by testing the functionality of the logic circuitry.
Therefore, what is needed is a new method of providing an addressable test structure with a small test pad area so that location of defects on a wafer can be easily determined.


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Kelvin Yih-Yuh Doong, et al., “Defect Detection for Short-loop Process and SRAM-Cell Optimization by Using Addressable Failure Site Test Structures (AFS-TS)”, SPIE'sInternational Symposium on Advanced Microelectronic Manufacturing and Nanotechnologies, Mar., 2002, Santa Clara, California.
Kelvin Yih-Yuh Doong, et. al., “The Short-Loop Process Tuning & Yield Evaluation by Using the Addressable Failure Site Test Structures (AFS-TS)”,Proc IEEE Int. Symp. Semiconductor Manufacturing (ISSM),pp. 165-198, Oct. 2000.
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