Method and data processing system for verifying circuit test vec

Details Method and data processing system for verifying circuit test vec Method and data processing system for verifying circuit test vec

1994-05-31

1997-02-04

Canney, Vincent P.

Excavating

39518309, 371 27, G06F 1100

Patent

active

056007876

ABSTRACT:
A test vector system (157) and method for generating and verifying test vectors for testing integrated circuit speed paths involves accessing a circuit model (160), a list of circuit paths (162) and a test vector verifier (165). A single circuit path, referred to as a selected path, is selected from the paths (162). Once logical constraints are set, hazard-free logical values and logical values for both the second test clock cycle and the first test clock cycle are justified. Test vectors are generated in response to the justified values and the test vectors are used as input to the test vector verifier. The test verifier produces patterns that provide robust delay path fault tests for the given path. The test patterns are serially shifted and double-clocked in an integrated circuit or electrical circuit manufactured in accordance with circuit model (160) to determine time delay path faults.

REFERENCES:
patent: 5056094 (1991-10-01), Whetsel
patent: 5291495 (1994-03-01), Udell, Jr.

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