Excavating
Patent
1994-03-28
1996-05-14
Voeltz, Emanuel T.
Excavating
371 213, 371 215, 364578, G06F 11263
Patent
active
055175066
ABSTRACT:
A test vector generator system (157) and method for generating test vectors for testing integrated circuit speed paths involves accessing both a circuit model (160) and a list of circuit paths (162). A single circuit path, referred to as a selected path, is selected from the paths (162). A set of logic value constraints is set for custom logic blocks, through the use of Boolean differences, and a set of logic value constraints is set for standard logic devices in the selected circuit path. These logical constraints are set to ensure that a proper input-to-output transition, which is used to identify speed path faults, results in response to only two clock cycles. Once logical constraints are set, hazard-free logical values and logical values for both the second test clock cycle and the first test clock cycle are justified. Test vectors are generated in response to the justified values and the test vectors are serially shifted and double-clocked in an integrated circuit or electrical circuit manufactured in accordance with circuit model (160) to determine time delay path faults.
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Kang Sung-ho
Konuk Haluk
Law Wai-on
Underwood Wilburn C.
Motorola Inc.
Voeltz Emanuel T.
Wachsman Hal D.
Witek Keith E.
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