Data processing: structural design – modeling – simulation – and em – Emulation – Compatibility emulation
Reexamination Certificate
2000-06-15
2004-07-13
Broda, Samuel (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Emulation
Compatibility emulation
C703S026000, C712S227000, C711S203000, C709S241000
Reexamination Certificate
active
06763328
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to processor emulation software, and more specifically to virtual memory paging during emulation of a target multiprocessor system.
BACKGROUND OF THE INVENTION
Emulating a first computer architecture on a second computer architecture is a well known technique in the area of data processing. It is becoming more common as the cost of developing new generation computer architectures continues to escalate. A program, called an “Emulator”, on a data processing system with the second computer architecture executes code designed for the first computer architecture: in essence pretending that it has the first computer architecture. The computer system having the second computer architecture and that executes the Emulator program is termed the “Host” computer system. A virtual computer system having the first (“emulated”) computer architecture is termed the “Target” system. Often both Target user and operating system software is executed together by the Emulator on the Host system, with the Target operating system managing resources for the Target user programs.
The computer industry has seen increasing interest in Legacy Emulation on commodity-based platforms over the past few years, such as the Intel IA-64 architecture. Through the literature and other sources, we are aware of about ten companies with research and/or development projects in this area. A common experience among them is recognition that the cost of emulation limits the achievable performance to equivalence with mid-range mainframe systems at this time. Only two claims we have seen set expected fairly high performance and these assume changes to the target OS to reduce the amount of code actually emulated in performing services for the target applications.
In order to strictly emulate the hardware instruction set of the Target system, software must transform the memory addresses generated by the emulation of the Target machine into addresses on the Host machine. One very critical element of Emulator performance is the matter of address mapping between the Target and Host systems. In virtual memory architectures, this critical element is the translation of Target virtual addressees into Host virtual addresses.
FIG. 1
is a block diagram illustrating an illustrative multiprocessor Host system utilized to emulate a Target system with a narrower word size. In the preferred embodiment disclosed below, the Host system utilizes 64-bit words, whereas the Target system supports 36-bit words. A multiprocessor system is shown in order to provide the level of performance necessary to emulate large-scale enterprise level Target systems. The multiprocessor system
40
shows two (2) microprocessors
42
, each containing its own local cache memory
44
. Some examples of microprocessors include Pentium II and IA-64 microprocessors from Intel Corporation, PowerPC microprocessors from Motorola, Inc. and IBM, and SPARC processors from Sun Microsystems. The cache memory
44
is typically implemented as extremely high-speed static random access memory (SRAM). The cache memory
44
may be implemented on the same semiconductor die as the microprocessor
42
, or may be implemented as part of a multi-chip-module (MCM) with the microprocessor
42
. In any case, the cache memory
44
for each microprocessor
42
is dedicated to that microprocessor
42
. Note here that a single level of cache memory
44
is illustrative. Other cache memory configurations are within the scope of this invention. Note also that two microprocessors are shown. This is for illustrative purposes, and it is understood that the invention disclosed below envisions emulating a multiprocessor Target system on either a single processor or a multiprocessor Host system.
The two shown microprocessors
42
are coupled by and communicate over an intraprocessor bus
46
. One of the functions of this intraprocessor bus
46
is to allow the two microprocessors
42
to communicate sufficiently so as to maintain coherence between their respective cache memories
44
. A single bus has been shown. However, multiple busses are also within the scope of this invention.
Also coupled to the intraprocessor bus
46
is a Host bridge
50
. This provides communications between the microprocessors
42
and the remainder of the computer system
40
. Coupled to the Host Bridge
50
is Host memory
54
. This is typically Dynamic Random Access Memory (DRAM). However, other types of memory may be utilized, including SRAM. Host memories
54
typically contain several orders of magnitude more memory than the cache memories
44
.
Also coupled to the Host Bridge
50
is a system bus
60
. The system bus
60
is utilized to couple the system
40
to lower speed peripheral devices. These lower speed peripheral devices can include display monitors, keyboards, communications devices, and the like (not shown here). Also coupled to the system bus are disk drives and other forms of storage capable of permanently storing data for the computer system
40
. Shown in this figure are a Host disk drive
62
and a Target disk drive
68
. The Host disk drive
62
typically contains the software required to emulate the Target system on the Host system. The Target disk drive
68
contains the software being emulated. It should be noted that the Host disk drive
62
is shown distinct from the Target disk drive
68
. Additionally, only a single Host disk drive
62
and Target disk drive
68
are shown. It is shown this way for illustrative purposes. However, the present invention also envisions combining the two on shared drives. It must also be noted that the Target disk drive
68
will often actually consist of a large number of different physical disk drives. This is especially true when Host systems capable of supporting enterprise level databases are emulated.
Memory is considered herein a relatively high speed machine readable medium and includes Volatile Memories, such as DRAM
54
, and SRAM
44
, and Non-Volatile Memories (not shown) such as, ROM, FLASH, EPROM, EEPROM, and bubble memory. Secondary Storage
62
,
68
includes machine-readable media such as hard disk drives, magnetic drum, and bubble memory. External Storage (not shown) includes machine-readable media such as floppy disks, removable hard drives, magnetic tape, CD-ROM, and even other computers, possibly connected via a communications line. The distinction drawn here between Secondary Storage
62
,
68
and External Storage is primarily for convenience in describing the invention. As such, it should be appreciated that there is substantial functional overlap between these elements. Computer software such as Target emulation software and user programs can be stored in a Computer Software Storage Medium, such as Memory
44
,
54
, Secondary Storage
62
,
68
, and External Storage. Executable versions of computer software cane be read from a Non-Volatile Storage Medium such as External Storage (not shown), Secondary Storage
62
,
68
, and Non-Volatile Memory (not shown), and loaded for execution directly into Volatile Memory
44
,
54
, executed directly out of Non-Volatile Memory, or stored on the Secondary Storage
62
,
68
prior to loading into Volatile Memory
44
,
54
for execution.
Virtual memory provides a processor with an apparent or virtual memory address space typically much larger than the real memory actually employed. It also allows provides a contiguous address space employing discontiguous real memory pages. In the GCOS® 8 environment, this capability consists of a directly addressable virtual space of 2**43 bytes and the mechanisms for translating this virtual memory address into a real memory address.
The remainder of the Background section discusses virtual memory addressing in the GCOS 8 environment sold by assignee of this invention. In order to provide for virtual memory management, assignment, and control, the 2**43-byte virtual memory space is divided into smaller units called “Working Spaces” and segments. The 2**43 bytes of virtual memory space are divided into 512 2
Bohult Stefan R.
Egolf David A.
Farmer Chad
Noyes Bruce A.
Broda Samuel
Bull HN Information Systems Inc.
Driscoll Faith F.
Hayden Bruce E.
LandOfFree
Method and data processing system for emulating virtual... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and data processing system for emulating virtual..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and data processing system for emulating virtual... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3199251