Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2001-10-31
2004-06-15
Phan, Trong (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S203000
Reexamination Certificate
active
06751152
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a memory array architecture which allows a lower wordline boosted voltage (V
pp
) operation while increasing the available sensing signal with an access transistor threshold voltage. A low V
pp
wordline operation results in a reduction in power consumption by saving power on Vpp generator support circuits, and a reduction in the size of the Vpp generator and support circuits, and also eliminates high Vpp voltage related problems such as dielectric breakdown and other reliability concerns while avoiding a complex decoding scheme and saving costs.
2. Discussion of the Prior Art
The evolution of submicron CMOS technology has resulted in a significant improvement in microprocessor speeds. Quadrupling roughly every three years, microprocessor speeds have now even exceeded 1 Ghz. Along with these advances in microprocessor technology have come more advanced software and multimedia applications, requiring larger memories for the applications thereof. Accordingly, there is an increasing demand for memories with higher density and performance. Today's multimedia computers require at least 641~28 MB, which increases the relative cost of the memories within the computer. In the near future, 256 MB or 1 GB computers will become commonplace, which suggests a potentially strong demand for 1 Gb DRAMs (Dynamic Random Access Memory) and beyond. Despite the huge size of the memory arrays and the lithographic difficulties that ensue, it is more important then ever to increase the manufacturing yield and reliability of the memory devices and memory systems containing a plurality of DRAMs. Process engineers constantly struggle to reduce and ultimately eliminate defects to improve yields and reliability. A significant cause of yield and reliability problems are failures due to a high voltage device stress.
Memory cells in a DRAM are typically accessed by boosting the wordline voltage (Vpp) to be higher than the voltage supply (Vdd). Therefore, access gates of the cells, wordline drivers, and their high voltage generator circuitry are key to improve device yield and reliability. For example, for a 1 Gb stand-alone conventional DRAM, for a Vdd of 2V, Vpp must be 3.3V or higher.
The reasons for such a high boosted Vpp voltage are:
(1) Conventional DRAMs use only the capacitive charge stored in the cell, which requires a higher voltage level to transfer a physical 1 data charge to the bitline, otherwise the read speed for reading a physical 1 data from the cell is degraded.
(2) For a write operation, the Vpp level should be higher than the voltage supply Vdd by at least the threshold voltage (Vth) of the access gate transistor to avoid a threshold voltage drop for writing a physical 1 data bit to the cell.
(3) The data stored in a DRAM memory cell is destroyed after a read operation. In order to restore the data to the cell after data sensing in a read operation, a write-back operation using a boosted Vpp voltage is needed to avoid the Vthn voltage drop. Increasing the boosted wordline voltage Vpp may be preferable to enhance the write back speed.
(4) In a conventional DRAM array, in order to prevent sub-threshold leakage and to maintain the memory cell retention quality, a transfer device (access gate transistor) with a high threshold voltage Vthn (i.e. 0.7V to 1.2V) is required. In order to perform a full signal write operation, a high Vpp is critical. In short, in a conventional DRAM array, if the Vpp level is not sufficient, the physical “1” signal stored in the cell is degraded which eventually leads to a data retention problem.
The drawbacks of using a boosted Vpp are:
(1) A requirement for a high efficiency charge pump to provide a Vpp level with a sufficient current supply. This becomes harder and harder as the Vdd level is continuously reduced corresponding to improved technology scaling. The pumping efficiency of a Vpp generator is drastically reduced when Vdd is less than 1.5V. Sometimes, to get a high Vpp level (>2.2V), a cascaded pump configuration, or two groups of pumps connected in series, is used. This means more power consumption, and also certainly more chip area.
(2) A high Vpp level causes reliability concerns on the gate dielectrics of devices having high Vpp stress. These devices include decoders, wordline drivers, multiplexers, level-shifters, and some critical devices in the charge pumps, etc.
(3) A larger chip size is needed in order to provide the stressed devices which have a longer channel length and a wider channel width. To minimize the stress, sometimes extra buffer devices, level shifters, etc. are added, all of which result in a larger chip area and increased process complexity.
(4) Furthermore, in order to minimize the stress, a thicker gate oxide and a special timing for WL decoding are necessary, which result in increased design/process complexity, degraded performance and higher cost.
The prior art detects a data bit in a memory cell by detecting first or second states of the cell voltage (0 or 1). The drawback of this method is that the sensing signal depends on both the first and second states stored in the cell. If the wordline WL is not boosted, the second state 1 has less voltage, thus reducing the available sensing signal (the voltage difference between the first and second states).
SUMMARY OF THE INVENTION
Accordingly, it is a primary object of the present invention to provide a DRAM memory array architecture which allows a low V
pp
wordline operation.
A further object of the subject invention is to significantly reduce the V
pp
(boosted wordline voltage) level, or to completely eliminate a high V
pp
level from a DRAM memory array.
Another object of the present invention is to provide a scheme to reduce Vpp to as low as 1.6V for a write operation and 1.2V for a read operation, while still achieving high performance read/write operations.
A further object of the subject invention is to provide a low Vpp architecture while maintaining or even increasing the available sensing signal.
Another object of the present invention is to eliminate high Vpp voltage related problems, such as dielectric breakdown and other reliability concerns, to significantly reduce the size of support circuits, to avoid a complex decoding scheme, and to save cost.
The present invention detects a data bit in the cell by transferring the first state 0 to the bitline BL. The cell voltage transfer of the second state is limited by using a low Vpp in a read mode. A data bit can be sensed by detecting the BL voltage after the signal development, which depends on only the first data bit state voltage. Therefore even if the wordline WL is not boosted, the signal is not lost as long as the first state 0 can be fully written to or read from the cell.
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Konishi, Yasuhiro, et al. (1989) “Analysis of Coupling Noise Between Adjacent Bit Lines in Megabit DRAM's”,IEEE Journal of Solid State Circuits 24(1): 35-41.
Nakano, H., et al., (1996) “A Dual Layer Bitline DRAM Array With Vcc/Vss Hybrid Precharge for Multi-Gigabit DRAM's”,Symposium on VLSI Circuits of Technical Papers 18(1):190-191; and.
Sato, Hirotoshi, et al. (1998) “A 5-MHz, 3.6-3m W, 1.4-V SRAM With Nonboosted, Vertical Bipolar Bit-Line Contact Memory Cell”,IEEE Journal of Solid-State Circuits 33(11): 1672-1681.
Hsu Louis L.
Kirihata Toshiaki K.
Storaska Daniel W.
International Business Machines - Corporation
Scully Scott Murphy & Presser
Walsh, Esq. Robert A.
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