Method and configuration for testing electronic circuits and int

Details Method and configuration for testing electronic circuits and int Method and configuration for testing electronic circuits and int

1989-09-29

1990-06-26

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 8, 437209, 437211, H01L 2166, H01L 2170

Patent

active

049372033

ABSTRACT:
The utilization of a removable overlay layer together with its associated metallization pattern, is used to effectively provide wafer scale integration for integrated circuit chips. The method and configuration of the present invention provide for the fabrication and testing of systems which are otherwise untestable. The present invention also permits integrated circuit systems to be tested in their final configuration in terms of speed and operating environment and the invention eliminates many of the problems associated with wafer or chip probes. The present invention also utilizes special test chips which are either temporarily or permanently affixed in an integrated circuit chip package.

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