Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Timing
Reexamination Certificate
2005-12-13
2005-12-13
Homere, Jean R. (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Timing
C703S002000, C703S013000, C702S117000, C716S030000
Reexamination Certificate
active
06975979
ABSTRACT:
To calculate pin-to-pin delay time, which is delay time from the input pin to the output pin of a logic block, and block-to-block delay time, which is delay time from an output pin of one block to an input pin of the next block, firstly, the pin-to-pin delay time and the block-to-block delay time are calculated with negligence in aging caused by a hot carrier effect, secondly, degradations caused by aged transistors connected to the input pin and the output pin, and lastly, the pin-to-pin delay time and block-to-block delay time are modified by the degradation rate.
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Translated copy of “Reason For Rejection”, Japanese Office Action, Jul. 12, 2000.
Akimoto Tetsuya
Hirata Morihisa
Day Herng-der
Homere Jean R.
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