Semiconductor device manufacturing: process – Chemical etching – Liquid phase etching
Reexamination Certificate
2001-11-30
2003-04-01
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Liquid phase etching
C438S754000
Reexamination Certificate
active
06541390
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to methods of semiconductor fabrication. More particularly, the present invention relates to etching methods which remove materials in the presence of cobalt silicide.
BACKGROUND OF THE INVENTION
Metal Oxide Semiconductor (MOS) devices are widely used in integrated circuit devices. Such MOS devices may include memory devices which are comprised of an array of memory cells. Each memory cell is comprised of a capacitor, on which the charge stored represents the logical state of the memory cell. Conductors, referred to as word lines, serve as gate electrodes of multiple access transistors which provide access to the memory cells. In a DRAM (Dynamic Random Access Memory), a word line typically is fabricated on a p-type silicon substrate coated with a thin film of silicon dioxide, known as the gate oxide. Word lines conventionally are formed on the gate oxide layer as a two-layer stack, typically including polysilicon and a conductor material such as tungsten silicide or titanium silicide (commonly referred to as a polycide word line). Further, polycide structures are also used for local interconnects in MOS devices. For example, such polycide structures may be used for the local interconnection of gates and drains in a SRAM (Static Random Access Memory).
Minimizing resistivity throughout the word line or other interconnect structures is of importance to meet the need of reducing time constants and allowing access of memory cells in as short a time period as possible. As memory density increases, feature sizes, including line sizes, decrease. For example, when the feature size of a conductor, such as a local interconnect or a word line, is reduced in a high density memory, the Kelvin contact resistance of the conductor increases. Thin tungsten silicide and titanium silicide are larger grain materials that contribute to a very rough silicide/silicon interface. As such, it reduces the effective ohmic contact area. Therefore, it is desirable to utilize conductors that have smaller grain sizes and as such, whose resistivity will not significantly increase for the same feature dimensions.
Cobalt silicide (CoSi
2
) is a suitable conductor material for the local interconnect and word line applications. Cobalt silicide is a fine grained material having a low bulk resistivity. Cobalt silicide is therefore, well suited for conductor applications, such as word line, local interconnect, bit line, or other conductor applications in the fabrication of MOS devices. However, cobalt silicide can be difficult to pattern using conventional dry etch processes because such processes produce nonvolatile cobalt fluorides and chlorides. Further, conventional methods of patterning cobalt silicide word lines such as for DRAMs may require extra masks to pattern insulating layers or spacers used in the fabrication of such memories.
Therefore, there is a need for methods of etching in the fabrication of stacks including cobalt silicide, e.g., word lines and local interconnects, which overcome the disadvantages described above, along with other problems as will be apparent from the description below. For example, the etch methods should be suitable for patterning deep submicron cobalt silicide lines resulting in straight sidewalls for such structures.
SUMMARY OF THE INVENTION
An etching method for use in integrated circuit fabrication according to the present invention includes providing a metal nitride layer on a substrate assembly, providing regions of cobalt silicide on first portions of the metal nitride layer, and providing regions of cobalt on second portions of the metal nitride layer. The regions of cobalt and the second portions of the metal nitride layer are removed with at least one solution including a mineral acid and a peroxide.
In various embodiments of the method, the mineral acid may be selected from the group including HCl, H
2
SO
4
, H
3
PO
4
, HNO
3
, and dilute HF (preferably the mineral acid is HCl); the peroxide may be hydrogen peroxide; the removing step may include removing the regions of cobalt and the second portions of the metal nitride layer with a single solution including a mineral acid and a peroxide; and/or the removing step may include the two steps of removing the regions of cobalt with a first solution containing a mineral acid and a peroxide and removing the second portions of the metal nitride layer with a second solution containing a peroxide.
In another method according to the present invention for use in patterning a stack including cobalt silicide, the method includes providing a layer of cobalt, regions of silicon, and a conductive diffusion barrier. The layer of cobalt and regions of silicon are reacted using thermal processing resulting in the stack including cobalt silicide and the conductive diffusion barrier and further resulting in unreacted cobalt overlying removable regions of the conductive diffusion barrier. The unreacted cobalt and removable regions of the conductive diffusion barrier are removed using at least one solution including a mineral acid and a peroxide.
An etching composition according to the present invention includes a mineral acid and a peroxide. Preferably, the mineral acid is HCl and the peroxide is hydrogen peroxide. More preferably, the composition includes a ratio in the range of about 1:1:35 (mineral acid:peroxide:deionized water) to about 1:1:5 (mineral acid:peroxide:deionized water).
Further, the above generally described methods may be used in forming structures such as word lines, gate electrodes, local interconnects, etc.
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Hu Yongjun Jeff
Lee Whonchee
Deo Duy Vu
Micron Technologies, Inc.
Mueting Raasch & Gebhardt, P.A.
Utech Benjamin L.
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